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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
792 lines
23 KiB
TableGen
792 lines
23 KiB
TableGen
//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===------------------------------------------------------------===//
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include "llvm/TableGen/SearchableTable.td"
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include "llvm/Target/Target.td"
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include "AMDGPUFeatures.td"
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class BoolToList<bit Value> {
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list<int> ret = !if(Value, [1]<int>, []<int>);
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}
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//===------------------------------------------------------------===//
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// Subtarget Features (device properties)
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//===------------------------------------------------------------===//
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def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
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"FastFMAF32",
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"true",
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"Assuming f32 fma is at least as fast as mul + add"
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>;
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def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
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"MIMG_R128",
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"true",
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"Support 128-bit texture resources"
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>;
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def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
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"HalfRate64Ops",
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"true",
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"Most fp64 instructions are half rate instead of quarter"
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>;
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def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
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"FlatAddressSpace",
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"true",
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"Support flat address space"
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>;
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def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
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"FlatInstOffsets",
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"true",
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"Flat instructions have immediate offset addressing mode"
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>;
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def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
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"FlatGlobalInsts",
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"true",
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"Have global_* flat memory instructions"
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>;
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def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
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"FlatScratchInsts",
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"true",
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"Have scratch_* flat memory instructions"
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>;
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def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
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"AddNoCarryInsts",
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"true",
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"Have VALU add/sub instructions without carry out"
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>;
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def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
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"UnalignedBufferAccess",
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"true",
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"Support unaligned global loads and stores"
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>;
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def FeatureTrapHandler: SubtargetFeature<"trap-handler",
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"TrapHandler",
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"true",
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"Trap handler support"
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>;
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def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
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"UnalignedScratchAccess",
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"true",
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"Support unaligned scratch loads and stores"
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>;
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def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
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"HasApertureRegs",
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"true",
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"Has Memory Aperture Base and Size Registers"
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>;
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def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
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"HasMadMixInsts",
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"true",
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"Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
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>;
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def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
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"HasFmaMixInsts",
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"true",
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"Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
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>;
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// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
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// XNACK. The current default kernel driver setting is:
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// - graphics ring: XNACK disabled
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// - compute ring: XNACK enabled
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//
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// If XNACK is enabled, the VMEM latency can be worse.
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// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
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def FeatureXNACK : SubtargetFeature<"xnack",
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"EnableXNACK",
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"true",
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"Enable XNACK support"
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>;
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def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
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"SGPRInitBug",
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"true",
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"VI SGPR initialization bug requiring a fixed SGPR allocation size"
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>;
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class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
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"ldsbankcount"#Value,
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"LDSBankCount",
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!cast<string>(Value),
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"The number of LDS banks per compute unit."
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>;
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def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
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def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
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def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
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"GCN3Encoding",
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"true",
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"Encoding format for VI"
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>;
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def FeatureCIInsts : SubtargetFeature<"ci-insts",
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"CIInsts",
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"true",
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"Additional instructions for CI+"
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>;
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def FeatureVIInsts : SubtargetFeature<"vi-insts",
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"VIInsts",
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"true",
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"Additional instructions for VI+"
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>;
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def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
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"GFX9Insts",
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"true",
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"Additional instructions for GFX9+"
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>;
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def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
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"HasSMemRealTime",
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"true",
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"Has s_memrealtime instruction"
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>;
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def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
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"HasInv2PiInlineImm",
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"true",
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"Has 1 / (2 * pi) as inline immediate"
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>;
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def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
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"Has16BitInsts",
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"true",
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"Has i16/f16 instructions"
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>;
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def FeatureVOP3P : SubtargetFeature<"vop3p",
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"HasVOP3PInsts",
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"true",
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"Has VOP3P packed instructions"
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>;
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def FeatureMovrel : SubtargetFeature<"movrel",
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"HasMovrel",
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"true",
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"Has v_movrel*_b32 instructions"
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>;
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def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
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"HasVGPRIndexMode",
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"true",
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"Has VGPR mode register indexing"
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>;
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def FeatureScalarStores : SubtargetFeature<"scalar-stores",
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"HasScalarStores",
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"true",
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"Has store scalar memory instructions"
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>;
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def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
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"HasScalarAtomics",
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"true",
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"Has atomic scalar memory instructions"
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>;
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def FeatureSDWA : SubtargetFeature<"sdwa",
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"HasSDWA",
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"true",
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"Support SDWA (Sub-DWORD Addressing) extension"
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>;
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def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
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"HasSDWAOmod",
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"true",
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"Support OMod with SDWA (Sub-DWORD Addressing) extension"
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>;
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def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
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"HasSDWAScalar",
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"true",
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"Support scalar register with SDWA (Sub-DWORD Addressing) extension"
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>;
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def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
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"HasSDWASdst",
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"true",
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"Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
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>;
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def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
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"HasSDWAMac",
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"true",
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"Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
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>;
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def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
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"HasSDWAOutModsVOPC",
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"true",
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"Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
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>;
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def FeatureDPP : SubtargetFeature<"dpp",
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"HasDPP",
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"true",
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"Support DPP (Data Parallel Primitives) extension"
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>;
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def FeatureR128A16 : SubtargetFeature<"r128-a16",
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"HasR128A16",
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"true",
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"Support 16 bit coordindates/gradients/lod/clamp/mip types on gfx9"
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>;
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def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
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"HasIntClamp",
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"true",
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"Support clamp for integer destination"
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>;
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def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
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"HasUnpackedD16VMem",
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"true",
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"Has unpacked d16 vmem instructions"
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>;
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def FeatureDLInsts : SubtargetFeature<"dl-insts",
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"HasDLInsts",
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"true",
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"Has v_fmac_f32 and v_xnor_b32 instructions"
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>;
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def FeatureDotInsts : SubtargetFeature<"dot-insts",
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"HasDotInsts",
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"true",
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"Has v_dot* instructions"
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>;
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def FeatureSRAMECC : SubtargetFeature<"sram-ecc",
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"EnableSRAMECC",
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"true",
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"Enable SRAM ECC"
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>;
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//===------------------------------------------------------------===//
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// Subtarget Features (options and debugging)
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//===------------------------------------------------------------===//
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// Denormal handling for fp64 and fp16 is controlled by the same
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// config register when fp16 supported.
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// TODO: Do we need a separate f16 setting when not legal?
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def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
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"FP64FP16Denormals",
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"true",
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"Enable double and half precision denormal handling",
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[FeatureFP64]
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>;
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def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
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"FP64FP16Denormals",
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"true",
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"Enable double and half precision denormal handling",
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[FeatureFP64, FeatureFP64FP16Denormals]
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>;
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def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
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"FP64FP16Denormals",
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"true",
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"Enable half precision denormal handling",
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[FeatureFP64FP16Denormals]
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>;
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def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
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"FPExceptions",
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"true",
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"Enable floating point exceptions"
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>;
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class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
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"max-private-element-size-"#size,
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"MaxPrivateElementSize",
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!cast<string>(size),
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"Maximum private access size may be "#size
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>;
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def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
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def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
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def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
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def FeatureEnableHugePrivateBuffer : SubtargetFeature<
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"huge-private-buffer",
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"EnableHugePrivateBuffer",
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"true",
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"Enable private/scratch buffer sizes greater than 128 GB"
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>;
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def FeatureDumpCode : SubtargetFeature <"DumpCode",
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"DumpCode",
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"true",
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"Dump MachineInstrs in the CodeEmitter"
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>;
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def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
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"DumpCode",
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"true",
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"Dump MachineInstrs in the CodeEmitter"
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>;
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// XXX - This should probably be removed once enabled by default
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def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
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"EnableLoadStoreOpt",
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"true",
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"Enable SI load/store optimizer pass"
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>;
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// Performance debugging feature. Allow using DS instruction immediate
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// offsets even if the base pointer can't be proven to be base. On SI,
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// base pointer values that won't give the same result as a 16-bit add
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// are not safe to fold, but this will override the conservative test
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// for the base pointer.
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def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
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"unsafe-ds-offset-folding",
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"EnableUnsafeDSOffsetFolding",
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"true",
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"Force using DS instruction immediate offsets on SI"
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>;
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def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
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"EnableSIScheduler",
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"true",
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"Enable SI Machine Scheduler"
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>;
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def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
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"EnableDS128",
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"true",
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"Use ds_{read|write}_b128"
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>;
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// Sparse texture support requires that all result registers are zeroed when
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// PRTStrictNull is set to true. This feature is turned on for all architectures
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// but is enabled as a feature in case there are situations where PRTStrictNull
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// is disabled by the driver.
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def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
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"EnablePRTStrictNull",
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"true",
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"Enable zeroing of result registers for sparse texture fetches"
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>;
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// Unless +-flat-for-global is specified, turn on FlatForGlobal for
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// all OS-es on VI and newer hardware to avoid assertion failures due
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// to missing ADDR64 variants of MUBUF instructions.
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// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
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// instructions.
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def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
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"FlatForGlobal",
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"true",
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"Force to generate flat instruction for global"
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>;
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def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
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"auto-waitcnt-before-barrier",
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"AutoWaitcntBeforeBarrier",
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"true",
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"Hardware automatically inserts waitcnt before barrier"
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>;
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def FeatureCodeObjectV3 : SubtargetFeature <
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"code-object-v3",
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"CodeObjectV3",
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"true",
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"Generate code object version 3"
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>;
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def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
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"HasTrigReducedRange",
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"true",
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"Requires use of fract on arguments to trig instructions"
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>;
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// Dummy feature used to disable assembler instructions.
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def FeatureDisable : SubtargetFeature<"",
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"FeatureDisable","true",
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"Dummy feature to disable assembler instructions"
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>;
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def FeatureGCN : SubtargetFeature<"gcn",
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"IsGCN",
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"true",
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"GCN or newer GPU"
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>;
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class GCNSubtargetFeatureGeneration <string Value,
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list<SubtargetFeature> Implies> :
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SubtargetFeatureGeneration <Value, "GCNSubtarget", Implies>;
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def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
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[FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
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FeatureWavefrontSize64, FeatureGCN,
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FeatureLDSBankCount32, FeatureMovrel, FeatureTrigReducedRange]
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>;
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def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
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[FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
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FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
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FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange]
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>;
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def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
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[FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
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FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
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FeatureGCN3Encoding, FeatureCIInsts, FeatureVIInsts, Feature16BitInsts,
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FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
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FeatureScalarStores, FeatureInv2PiInlineImm,
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FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
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FeatureIntClamp, FeatureTrigReducedRange
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]
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>;
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def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
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[FeatureFP64, FeatureLocalMemorySize65536,
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FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
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FeatureGCN3Encoding, FeatureCIInsts, FeatureVIInsts, Feature16BitInsts,
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FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
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FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
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FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
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FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
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FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
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FeatureAddNoCarryInsts, FeatureScalarAtomics, FeatureR128A16
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]
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>;
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class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
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list<SubtargetFeature> Implies>
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: SubtargetFeature <
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"isaver"#Major#"."#Minor#"."#Stepping,
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"IsaVersion",
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"ISAVersion"#Major#"_"#Minor#"_"#Stepping,
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"Instruction set version number",
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Implies
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>;
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def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
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[FeatureSouthernIslands,
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FeatureFastFMAF32,
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HalfRate64Ops,
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FeatureLDSBankCount32,
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FeatureCodeObjectV3]>;
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def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
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[FeatureSouthernIslands,
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FeatureLDSBankCount32,
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FeatureCodeObjectV3]>;
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def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
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[FeatureSeaIslands,
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FeatureLDSBankCount32,
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FeatureCodeObjectV3]>;
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def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
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[FeatureSeaIslands,
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HalfRate64Ops,
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FeatureLDSBankCount32,
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FeatureFastFMAF32,
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FeatureCodeObjectV3]>;
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def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
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[FeatureSeaIslands,
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FeatureLDSBankCount16,
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FeatureFastFMAF32,
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FeatureCodeObjectV3]>;
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def FeatureISAVersion7_0_3 : SubtargetFeatureISAVersion <7,0,3,
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|
[FeatureSeaIslands,
|
|
FeatureLDSBankCount16,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion7_0_4 : SubtargetFeatureISAVersion <7,0,4,
|
|
[FeatureSeaIslands,
|
|
FeatureLDSBankCount32,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
|
|
[FeatureVolcanicIslands,
|
|
FeatureFastFMAF32,
|
|
HalfRate64Ops,
|
|
FeatureLDSBankCount32,
|
|
FeatureXNACK,
|
|
FeatureUnpackedD16VMem,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
|
|
[FeatureVolcanicIslands,
|
|
FeatureLDSBankCount32,
|
|
FeatureSGPRInitBug,
|
|
FeatureUnpackedD16VMem,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
|
|
[FeatureVolcanicIslands,
|
|
FeatureLDSBankCount32,
|
|
FeatureUnpackedD16VMem,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
|
|
[FeatureVolcanicIslands,
|
|
FeatureLDSBankCount16,
|
|
FeatureXNACK,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
|
|
[FeatureGFX9,
|
|
FeatureMadMixInsts,
|
|
FeatureLDSBankCount32,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
|
|
[FeatureGFX9,
|
|
FeatureMadMixInsts,
|
|
FeatureLDSBankCount32,
|
|
FeatureXNACK,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion9_0_4 : SubtargetFeatureISAVersion <9,0,4,
|
|
[FeatureGFX9,
|
|
FeatureLDSBankCount32,
|
|
FeatureFmaMixInsts,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion9_0_6 : SubtargetFeatureISAVersion <9,0,6,
|
|
[FeatureGFX9,
|
|
HalfRate64Ops,
|
|
FeatureFmaMixInsts,
|
|
FeatureLDSBankCount32,
|
|
FeatureDLInsts,
|
|
FeatureDotInsts,
|
|
FeatureSRAMECC,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
def FeatureISAVersion9_0_9 : SubtargetFeatureISAVersion <9,0,9,
|
|
[FeatureGFX9,
|
|
FeatureMadMixInsts,
|
|
FeatureLDSBankCount32,
|
|
FeatureXNACK,
|
|
FeatureCodeObjectV3]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Debugger related subtarget features.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def FeatureDebuggerInsertNops : SubtargetFeature<
|
|
"amdgpu-debugger-insert-nops",
|
|
"DebuggerInsertNops",
|
|
"true",
|
|
"Insert one nop instruction for each high level source statement"
|
|
>;
|
|
|
|
def FeatureDebuggerEmitPrologue : SubtargetFeature<
|
|
"amdgpu-debugger-emit-prologue",
|
|
"DebuggerEmitPrologue",
|
|
"true",
|
|
"Emit debugger prologue"
|
|
>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def AMDGPUInstrInfo : InstrInfo {
|
|
let guessInstructionProperties = 1;
|
|
let noNamedPositionallyEncodedOperands = 1;
|
|
}
|
|
|
|
def AMDGPUAsmParser : AsmParser {
|
|
// Some of the R600 registers have the same name, so this crashes.
|
|
// For example T0_XYZW and T0_XY both have the asm name T0.
|
|
let ShouldEmitMatchRegisterName = 0;
|
|
}
|
|
|
|
def AMDGPUAsmWriter : AsmWriter {
|
|
int PassSubtarget = 1;
|
|
}
|
|
|
|
def AMDGPUAsmVariants {
|
|
string Default = "Default";
|
|
int Default_ID = 0;
|
|
string VOP3 = "VOP3";
|
|
int VOP3_ID = 1;
|
|
string SDWA = "SDWA";
|
|
int SDWA_ID = 2;
|
|
string SDWA9 = "SDWA9";
|
|
int SDWA9_ID = 3;
|
|
string DPP = "DPP";
|
|
int DPP_ID = 4;
|
|
string Disable = "Disable";
|
|
int Disable_ID = 5;
|
|
}
|
|
|
|
def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
|
|
let Variant = AMDGPUAsmVariants.Default_ID;
|
|
let Name = AMDGPUAsmVariants.Default;
|
|
}
|
|
|
|
def VOP3AsmParserVariant : AsmParserVariant {
|
|
let Variant = AMDGPUAsmVariants.VOP3_ID;
|
|
let Name = AMDGPUAsmVariants.VOP3;
|
|
}
|
|
|
|
def SDWAAsmParserVariant : AsmParserVariant {
|
|
let Variant = AMDGPUAsmVariants.SDWA_ID;
|
|
let Name = AMDGPUAsmVariants.SDWA;
|
|
}
|
|
|
|
def SDWA9AsmParserVariant : AsmParserVariant {
|
|
let Variant = AMDGPUAsmVariants.SDWA9_ID;
|
|
let Name = AMDGPUAsmVariants.SDWA9;
|
|
}
|
|
|
|
|
|
def DPPAsmParserVariant : AsmParserVariant {
|
|
let Variant = AMDGPUAsmVariants.DPP_ID;
|
|
let Name = AMDGPUAsmVariants.DPP;
|
|
}
|
|
|
|
def AMDGPU : Target {
|
|
// Pull in Instruction Info:
|
|
let InstructionSet = AMDGPUInstrInfo;
|
|
let AssemblyParsers = [AMDGPUAsmParser];
|
|
let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
|
|
VOP3AsmParserVariant,
|
|
SDWAAsmParserVariant,
|
|
SDWA9AsmParserVariant,
|
|
DPPAsmParserVariant];
|
|
let AssemblyWriters = [AMDGPUAsmWriter];
|
|
let AllowRegisterRenaming = 1;
|
|
}
|
|
|
|
// Dummy Instruction itineraries for pseudo instructions
|
|
def ALU_NULL : FuncUnit;
|
|
def NullALU : InstrItinClass;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Predicate helper class
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def isSICI : Predicate<
|
|
"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
|
|
"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
|
|
>, AssemblerPredicate<"!FeatureGCN3Encoding">;
|
|
|
|
def isVI : Predicate <
|
|
"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
|
|
AssemblerPredicate<"FeatureGCN3Encoding">;
|
|
|
|
def isGFX9 : Predicate <
|
|
"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
|
|
AssemblerPredicate<"FeatureGFX9Insts">;
|
|
|
|
// TODO: Either the name to be changed or we simply use IsCI!
|
|
def isCIVI : Predicate <
|
|
"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
|
|
AssemblerPredicate<"FeatureCIInsts">;
|
|
|
|
def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
|
|
AssemblerPredicate<"FeatureFlatAddressSpace">;
|
|
|
|
def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
|
|
AssemblerPredicate<"FeatureFlatGlobalInsts">;
|
|
def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
|
|
AssemblerPredicate<"FeatureFlatScratchInsts">;
|
|
def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
|
|
AssemblerPredicate<"FeatureGFX9Insts">;
|
|
|
|
def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
|
|
AssemblerPredicate<"FeatureUnpackedD16VMem">;
|
|
def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
|
|
AssemblerPredicate<"!FeatureUnpackedD16VMem">;
|
|
|
|
def D16PreservesUnusedBits :
|
|
Predicate<"Subtarget->hasD16LoadStore() && !Subtarget->isSRAMECCEnabled()">,
|
|
AssemblerPredicate<"FeatureGFX9Insts,!FeatureSRAMECC">;
|
|
|
|
def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
|
|
def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
|
|
|
|
def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
|
|
AssemblerPredicate<"FeatureGFX9Insts">;
|
|
|
|
def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
|
|
AssemblerPredicate<"FeatureAddNoCarryInsts">;
|
|
|
|
def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">,
|
|
AssemblerPredicate<"!FeatureAddNoCarryInsts">;
|
|
|
|
def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
|
|
AssemblerPredicate<"Feature16BitInsts">;
|
|
def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
|
|
AssemblerPredicate<"FeatureVOP3P">;
|
|
|
|
def NotHasVOP3PInsts : Predicate<"!Subtarget->hasVOP3PInsts()">,
|
|
AssemblerPredicate<"!FeatureVOP3P">;
|
|
|
|
def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
|
|
AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
|
|
|
|
def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
|
|
AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
|
|
|
|
def HasDPP : Predicate<"Subtarget->hasDPP()">,
|
|
AssemblerPredicate<"FeatureDPP">;
|
|
|
|
def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
|
|
AssemblerPredicate<"FeatureR128A16">;
|
|
|
|
def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
|
|
AssemblerPredicate<"FeatureIntClamp">;
|
|
|
|
def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
|
|
AssemblerPredicate<"FeatureMadMixInsts">;
|
|
|
|
def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
|
|
AssemblerPredicate<"FeatureScalarAtomics">;
|
|
|
|
def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
|
|
def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
|
|
def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
|
|
AssemblerPredicate<"FeatureVGPRIndexMode">;
|
|
def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
|
|
AssemblerPredicate<"FeatureMovrel">;
|
|
|
|
def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
|
|
AssemblerPredicate<"FeatureFmaMixInsts">;
|
|
|
|
def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
|
|
AssemblerPredicate<"FeatureDLInsts">;
|
|
|
|
def HasDotInsts : Predicate<"Subtarget->hasDotInsts()">,
|
|
AssemblerPredicate<"FeatureDotInsts">;
|
|
|
|
|
|
def EnableLateCFGStructurize : Predicate<
|
|
"EnableLateStructurizeCFG">;
|
|
|
|
// Include AMDGPU TD files
|
|
include "SISchedule.td"
|
|
include "GCNProcessors.td"
|
|
include "AMDGPUInstrInfo.td"
|
|
include "AMDGPURegisterInfo.td"
|
|
include "AMDGPURegisterBanks.td"
|
|
include "AMDGPUInstructions.td"
|
|
include "SIInstrInfo.td"
|
|
include "AMDGPUCallingConv.td"
|
|
include "AMDGPUSearchableTables.td"
|