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446 lines
15 KiB
C++
446 lines
15 KiB
C++
//=======- GCNDPPCombine.cpp - optimization for DPP instructions ---==========//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// The pass combines V_MOV_B32_dpp instruction with its VALU uses as a DPP src0
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// operand.If any of the use instruction cannot be combined with the mov the
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// whole sequence is reverted.
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//
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// $old = ...
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// $dpp_value = V_MOV_B32_dpp $old, $vgpr_to_be_read_from_other_lane,
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// dpp_controls..., $bound_ctrl
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// $res = VALU $dpp_value, ...
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//
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// to
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//
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// $res = VALU_DPP $folded_old, $vgpr_to_be_read_from_other_lane, ...,
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// dpp_controls..., $folded_bound_ctrl
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//
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// Combining rules :
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//
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// $bound_ctrl is DPP_BOUND_ZERO, $old is any
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// $bound_ctrl is DPP_BOUND_OFF, $old is 0
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//
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// ->$folded_old = undef, $folded_bound_ctrl = DPP_BOUND_ZERO
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// $bound_ctrl is DPP_BOUND_OFF, $old is undef
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//
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// ->$folded_old = undef, $folded_bound_ctrl = DPP_BOUND_OFF
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// $bound_ctrl is DPP_BOUND_OFF, $old is foldable
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//
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// ->$folded_old = folded value, $folded_bound_ctrl = DPP_BOUND_OFF
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/Pass.h"
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#include <cassert>
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using namespace llvm;
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#define DEBUG_TYPE "gcn-dpp-combine"
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STATISTIC(NumDPPMovsCombined, "Number of DPP moves combined.");
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namespace {
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class GCNDPPCombine : public MachineFunctionPass {
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MachineRegisterInfo *MRI;
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const SIInstrInfo *TII;
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using RegSubRegPair = TargetInstrInfo::RegSubRegPair;
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MachineOperand *getOldOpndValue(MachineOperand &OldOpnd) const;
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RegSubRegPair foldOldOpnd(MachineInstr &OrigMI,
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RegSubRegPair OldOpndVGPR,
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MachineOperand &OldOpndValue) const;
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MachineInstr *createDPPInst(MachineInstr &OrigMI,
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MachineInstr &MovMI,
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RegSubRegPair OldOpndVGPR,
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MachineOperand *OldOpnd,
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bool BoundCtrlZero) const;
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MachineInstr *createDPPInst(MachineInstr &OrigMI,
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MachineInstr &MovMI,
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RegSubRegPair OldOpndVGPR,
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bool BoundCtrlZero) const;
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bool hasNoImmOrEqual(MachineInstr &MI,
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unsigned OpndName,
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int64_t Value,
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int64_t Mask = -1) const;
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bool combineDPPMov(MachineInstr &MI) const;
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public:
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static char ID;
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GCNDPPCombine() : MachineFunctionPass(ID) {
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initializeGCNDPPCombinePass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return "GCN DPP Combine"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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} // end anonymous namespace
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INITIALIZE_PASS(GCNDPPCombine, DEBUG_TYPE, "GCN DPP Combine", false, false)
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char GCNDPPCombine::ID = 0;
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char &llvm::GCNDPPCombineID = GCNDPPCombine::ID;
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FunctionPass *llvm::createGCNDPPCombinePass() {
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return new GCNDPPCombine();
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}
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static int getDPPOp(unsigned Op) {
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auto DPP32 = AMDGPU::getDPPOp32(Op);
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if (DPP32 != -1)
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return DPP32;
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auto E32 = AMDGPU::getVOPe32(Op);
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return E32 != -1 ? AMDGPU::getDPPOp32(E32) : -1;
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}
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// tracks the register operand definition and returns:
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// 1. immediate operand used to initialize the register if found
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// 2. nullptr if the register operand is undef
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// 3. the operand itself otherwise
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MachineOperand *GCNDPPCombine::getOldOpndValue(MachineOperand &OldOpnd) const {
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auto *Def = getVRegSubRegDef(getRegSubRegPair(OldOpnd), *MRI);
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if (!Def)
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return nullptr;
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switch(Def->getOpcode()) {
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default: break;
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case AMDGPU::IMPLICIT_DEF:
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return nullptr;
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case AMDGPU::COPY:
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case AMDGPU::V_MOV_B32_e32: {
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auto &Op1 = Def->getOperand(1);
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if (Op1.isImm())
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return &Op1;
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break;
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}
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}
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return &OldOpnd;
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}
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MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
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MachineInstr &MovMI,
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RegSubRegPair OldOpndVGPR,
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bool BoundCtrlZero) const {
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assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp);
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assert(TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg() ==
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TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0)->getReg());
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auto OrigOp = OrigMI.getOpcode();
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auto DPPOp = getDPPOp(OrigOp);
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if (DPPOp == -1) {
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LLVM_DEBUG(dbgs() << " failed: no DPP opcode\n");
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return nullptr;
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}
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auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI,
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OrigMI.getDebugLoc(), TII->get(DPPOp));
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bool Fail = false;
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do {
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auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst);
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assert(Dst);
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DPPInst.add(*Dst);
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int NumOperands = 1;
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const int OldIdx = AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::old);
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if (OldIdx != -1) {
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assert(OldIdx == NumOperands);
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assert(isOfRegClass(OldOpndVGPR, AMDGPU::VGPR_32RegClass, *MRI));
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DPPInst.addReg(OldOpndVGPR.Reg, 0, OldOpndVGPR.SubReg);
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++NumOperands;
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}
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if (auto *Mod0 = TII->getNamedOperand(OrigMI,
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AMDGPU::OpName::src0_modifiers)) {
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assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp,
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AMDGPU::OpName::src0_modifiers));
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assert(0LL == (Mod0->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG)));
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DPPInst.addImm(Mod0->getImm());
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++NumOperands;
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}
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auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);
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assert(Src0);
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if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) {
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LLVM_DEBUG(dbgs() << " failed: src0 is illegal\n");
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Fail = true;
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break;
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}
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DPPInst.add(*Src0);
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++NumOperands;
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if (auto *Mod1 = TII->getNamedOperand(OrigMI,
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AMDGPU::OpName::src1_modifiers)) {
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assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp,
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AMDGPU::OpName::src1_modifiers));
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assert(0LL == (Mod1->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG)));
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DPPInst.addImm(Mod1->getImm());
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++NumOperands;
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}
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if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) {
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if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) {
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LLVM_DEBUG(dbgs() << " failed: src1 is illegal\n");
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Fail = true;
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break;
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}
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DPPInst.add(*Src1);
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++NumOperands;
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}
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if (auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2)) {
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if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) {
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LLVM_DEBUG(dbgs() << " failed: src2 is illegal\n");
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Fail = true;
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break;
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}
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DPPInst.add(*Src2);
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}
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DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl));
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DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask));
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DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask));
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DPPInst.addImm(BoundCtrlZero ? 1 : 0);
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} while (false);
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if (Fail) {
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DPPInst.getInstr()->eraseFromParent();
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return nullptr;
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}
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LLVM_DEBUG(dbgs() << " combined: " << *DPPInst.getInstr());
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return DPPInst.getInstr();
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}
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GCNDPPCombine::RegSubRegPair
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GCNDPPCombine::foldOldOpnd(MachineInstr &OrigMI,
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RegSubRegPair OldOpndVGPR,
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MachineOperand &OldOpndValue) const {
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assert(OldOpndValue.isImm());
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switch (OrigMI.getOpcode()) {
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default: break;
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case AMDGPU::V_MAX_U32_e32:
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if (OldOpndValue.getImm() == std::numeric_limits<uint32_t>::max())
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return OldOpndVGPR;
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break;
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case AMDGPU::V_MAX_I32_e32:
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if (OldOpndValue.getImm() == std::numeric_limits<int32_t>::max())
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return OldOpndVGPR;
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break;
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case AMDGPU::V_MIN_I32_e32:
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if (OldOpndValue.getImm() == std::numeric_limits<int32_t>::min())
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return OldOpndVGPR;
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break;
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case AMDGPU::V_MUL_I32_I24_e32:
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case AMDGPU::V_MUL_U32_U24_e32:
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if (OldOpndValue.getImm() == 1) {
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auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
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assert(Src1 && Src1->isReg());
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return getRegSubRegPair(*Src1);
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}
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break;
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}
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return RegSubRegPair();
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}
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// Cases to combine:
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// $bound_ctrl is DPP_BOUND_ZERO, $old is any
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// $bound_ctrl is DPP_BOUND_OFF, $old is 0
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// -> $old = undef, $bound_ctrl = DPP_BOUND_ZERO
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// $bound_ctrl is DPP_BOUND_OFF, $old is undef
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// -> $old = undef, $bound_ctrl = DPP_BOUND_OFF
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// $bound_ctrl is DPP_BOUND_OFF, $old is foldable
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// -> $old = folded value, $bound_ctrl = DPP_BOUND_OFF
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MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
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MachineInstr &MovMI,
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RegSubRegPair OldOpndVGPR,
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MachineOperand *OldOpndValue,
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bool BoundCtrlZero) const {
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assert(OldOpndVGPR.Reg);
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if (!BoundCtrlZero && OldOpndValue) {
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assert(OldOpndValue->isImm());
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OldOpndVGPR = foldOldOpnd(OrigMI, OldOpndVGPR, *OldOpndValue);
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if (!OldOpndVGPR.Reg) {
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LLVM_DEBUG(dbgs() << " failed: old immediate cannot be folded\n");
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return nullptr;
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}
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}
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return createDPPInst(OrigMI, MovMI, OldOpndVGPR, BoundCtrlZero);
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}
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// returns true if MI doesn't have OpndName immediate operand or the
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// operand has Value
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bool GCNDPPCombine::hasNoImmOrEqual(MachineInstr &MI, unsigned OpndName,
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int64_t Value, int64_t Mask) const {
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auto *Imm = TII->getNamedOperand(MI, OpndName);
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if (!Imm)
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return true;
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assert(Imm->isImm());
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return (Imm->getImm() & Mask) == Value;
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}
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bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
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assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp);
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auto *BCZOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bound_ctrl);
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assert(BCZOpnd && BCZOpnd->isImm());
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bool BoundCtrlZero = 0 != BCZOpnd->getImm();
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LLVM_DEBUG(dbgs() << "\nDPP combine: " << MovMI);
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auto *OldOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::old);
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assert(OldOpnd && OldOpnd->isReg());
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auto OldOpndVGPR = getRegSubRegPair(*OldOpnd);
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auto *OldOpndValue = getOldOpndValue(*OldOpnd);
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assert(!OldOpndValue || OldOpndValue->isImm() || OldOpndValue == OldOpnd);
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if (OldOpndValue) {
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if (BoundCtrlZero) {
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OldOpndVGPR.Reg = AMDGPU::NoRegister; // should be undef, ignore old opnd
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OldOpndValue = nullptr;
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} else {
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if (!OldOpndValue->isImm()) {
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LLVM_DEBUG(dbgs() << " failed: old operand isn't an imm or undef\n");
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return false;
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}
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if (OldOpndValue->getImm() == 0) {
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OldOpndVGPR.Reg = AMDGPU::NoRegister; // should be undef
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OldOpndValue = nullptr;
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BoundCtrlZero = true;
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}
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}
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}
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LLVM_DEBUG(dbgs() << " old=";
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if (!OldOpndValue)
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dbgs() << "undef";
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else
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dbgs() << OldOpndValue->getImm();
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dbgs() << ", bound_ctrl=" << BoundCtrlZero << '\n');
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std::vector<MachineInstr*> OrigMIs, DPPMIs;
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if (!OldOpndVGPR.Reg) { // OldOpndVGPR = undef
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OldOpndVGPR = RegSubRegPair(
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MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass));
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auto UndefInst = BuildMI(*MovMI.getParent(), MovMI, MovMI.getDebugLoc(),
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TII->get(AMDGPU::IMPLICIT_DEF), OldOpndVGPR.Reg);
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DPPMIs.push_back(UndefInst.getInstr());
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}
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OrigMIs.push_back(&MovMI);
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bool Rollback = true;
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for (auto &Use : MRI->use_nodbg_operands(
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TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg())) {
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Rollback = true;
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auto &OrigMI = *Use.getParent();
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auto OrigOp = OrigMI.getOpcode();
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if (TII->isVOP3(OrigOp)) {
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if (!TII->hasVALU32BitEncoding(OrigOp)) {
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LLVM_DEBUG(dbgs() << " failed: VOP3 hasn't e32 equivalent\n");
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break;
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}
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// check if other than abs|neg modifiers are set (opsel for example)
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const int64_t Mask = ~(SISrcMods::ABS | SISrcMods::NEG);
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if (!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::src0_modifiers, 0, Mask) ||
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!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::src1_modifiers, 0, Mask) ||
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!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::clamp, 0) ||
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!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::omod, 0)) {
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LLVM_DEBUG(dbgs() << " failed: VOP3 has non-default modifiers\n");
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break;
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}
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} else if (!TII->isVOP1(OrigOp) && !TII->isVOP2(OrigOp)) {
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LLVM_DEBUG(dbgs() << " failed: not VOP1/2/3\n");
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break;
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}
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LLVM_DEBUG(dbgs() << " combining: " << OrigMI);
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if (&Use == TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0)) {
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if (auto *DPPInst = createDPPInst(OrigMI, MovMI, OldOpndVGPR,
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OldOpndValue, BoundCtrlZero)) {
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DPPMIs.push_back(DPPInst);
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Rollback = false;
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}
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} else if (OrigMI.isCommutable() &&
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&Use == TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) {
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auto *BB = OrigMI.getParent();
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auto *NewMI = BB->getParent()->CloneMachineInstr(&OrigMI);
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BB->insert(OrigMI, NewMI);
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if (TII->commuteInstruction(*NewMI)) {
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LLVM_DEBUG(dbgs() << " commuted: " << *NewMI);
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if (auto *DPPInst = createDPPInst(*NewMI, MovMI, OldOpndVGPR,
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OldOpndValue, BoundCtrlZero)) {
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DPPMIs.push_back(DPPInst);
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Rollback = false;
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}
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} else
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LLVM_DEBUG(dbgs() << " failed: cannot be commuted\n");
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NewMI->eraseFromParent();
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} else
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LLVM_DEBUG(dbgs() << " failed: no suitable operands\n");
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if (Rollback)
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break;
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OrigMIs.push_back(&OrigMI);
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}
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for (auto *MI : *(Rollback? &DPPMIs : &OrigMIs))
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MI->eraseFromParent();
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return !Rollback;
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}
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bool GCNDPPCombine::runOnMachineFunction(MachineFunction &MF) {
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auto &ST = MF.getSubtarget<GCNSubtarget>();
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if (!ST.hasDPP() || skipFunction(MF.getFunction()))
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return false;
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MRI = &MF.getRegInfo();
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TII = ST.getInstrInfo();
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assert(MRI->isSSA() && "Must be run on SSA");
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bool Changed = false;
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for (auto &MBB : MF) {
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for (auto I = MBB.rbegin(), E = MBB.rend(); I != E;) {
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auto &MI = *I++;
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if (MI.getOpcode() == AMDGPU::V_MOV_B32_dpp && combineDPPMov(MI)) {
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Changed = true;
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++NumDPPMovsCombined;
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}
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}
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}
|
|
return Changed;
|
|
}
|