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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
92 lines
3.4 KiB
C++
92 lines
3.4 KiB
C++
//===-- SystemZRegisterInfo.h - SystemZ register information ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZREGISTERINFO_H
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#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZREGISTERINFO_H
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#include "SystemZ.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#include "SystemZGenRegisterInfo.inc"
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namespace llvm {
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class LiveIntervals;
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namespace SystemZ {
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// Return the subreg to use for referring to the even and odd registers
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// in a GR128 pair. Is32Bit says whether we want a GR32 or GR64.
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inline unsigned even128(bool Is32bit) {
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return Is32bit ? subreg_hl32 : subreg_h64;
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}
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inline unsigned odd128(bool Is32bit) {
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return Is32bit ? subreg_l32 : subreg_l64;
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}
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} // end namespace SystemZ
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struct SystemZRegisterInfo : public SystemZGenRegisterInfo {
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public:
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SystemZRegisterInfo();
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is currently only used by LOAD_STACK_GUARD, which requires a non-%r0
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/// register, hence ADDR64.
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const TargetRegisterClass *
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getPointerRegClass(const MachineFunction &MF,
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unsigned Kind=0) const override {
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return &SystemZ::ADDR64BitRegClass;
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}
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/// getCrossCopyRegClass - Returns a legal register class to copy a register
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/// in the specified class to or from. Returns NULL if it is possible to copy
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/// between a two registers of the specified class.
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const TargetRegisterClass *
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getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
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bool getRegAllocationHints(unsigned VirtReg,
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ArrayRef<MCPhysReg> Order,
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SmallVectorImpl<MCPhysReg> &Hints,
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const MachineFunction &MF,
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const VirtRegMap *VRM,
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const LiveRegMatrix *Matrix) const override;
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// Override TargetRegisterInfo.h.
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bool requiresRegisterScavenging(const MachineFunction &MF) const override {
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return true;
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}
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bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
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return true;
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}
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bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
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return true;
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}
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const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID CC) const override;
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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void eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const override;
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/// SrcRC and DstRC will be morphed into NewRC if this returns true.
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bool shouldCoalesce(MachineInstr *MI,
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const TargetRegisterClass *SrcRC,
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unsigned SubReg,
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const TargetRegisterClass *DstRC,
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unsigned DstSubReg,
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const TargetRegisterClass *NewRC,
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LiveIntervals &LIS) const override;
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unsigned getFrameRegister(const MachineFunction &MF) const override;
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};
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} // end namespace llvm
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#endif
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