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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
505 lines
12 KiB
TableGen
505 lines
12 KiB
TableGen
//===-- R600InstrFormats.td - R600 Instruction Encodings ------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// R600 Instruction format definitions.
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//
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//===----------------------------------------------------------------------===//
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def isR600 : Predicate<"Subtarget->getGeneration() <= AMDGPUSubtarget::R700">;
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def isR600toCayman : Predicate<
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"Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS">;
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class R600Pat<dag pattern, dag result> : AMDGPUPat<pattern, result> {
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let SubtargetPredicate = isR600toCayman;
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}
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class InstR600 <dag outs, dag ins, string asm, list<dag> pattern,
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InstrItinClass itin = NoItinerary>
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: AMDGPUInst <outs, ins, asm, pattern>, PredicateControl {
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field bits<64> Inst;
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bit Trig = 0;
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bit Op3 = 0;
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bit isVector = 0;
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bits<2> FlagOperandIdx = 0;
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bit Op1 = 0;
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bit Op2 = 0;
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bit LDS_1A = 0;
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bit LDS_1A1D = 0;
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bit HasNativeOperands = 0;
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bit VTXInst = 0;
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bit TEXInst = 0;
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bit ALUInst = 0;
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bit IsExport = 0;
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bit LDS_1A2D = 0;
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let SubtargetPredicate = isR600toCayman;
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let Namespace = "R600";
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let OutOperandList = outs;
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let InOperandList = ins;
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let AsmString = asm;
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let Pattern = pattern;
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let Itinerary = itin;
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// No AsmMatcher support.
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let isCodeGenOnly = 1;
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let TSFlags{4} = Trig;
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let TSFlags{5} = Op3;
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// Vector instructions are instructions that must fill all slots in an
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// instruction group
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let TSFlags{6} = isVector;
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let TSFlags{8-7} = FlagOperandIdx;
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let TSFlags{9} = HasNativeOperands;
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let TSFlags{10} = Op1;
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let TSFlags{11} = Op2;
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let TSFlags{12} = VTXInst;
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let TSFlags{13} = TEXInst;
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let TSFlags{14} = ALUInst;
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let TSFlags{15} = LDS_1A;
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let TSFlags{16} = LDS_1A1D;
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let TSFlags{17} = IsExport;
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let TSFlags{18} = LDS_1A2D;
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}
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//===----------------------------------------------------------------------===//
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// ALU instructions
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//===----------------------------------------------------------------------===//
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class R600_ALU_LDS_Word0 {
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field bits<32> Word0;
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bits<11> src0;
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bits<1> src0_rel;
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bits<11> src1;
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bits<1> src1_rel;
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bits<3> index_mode = 0;
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bits<2> pred_sel;
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bits<1> last;
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bits<9> src0_sel = src0{8-0};
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bits<2> src0_chan = src0{10-9};
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bits<9> src1_sel = src1{8-0};
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bits<2> src1_chan = src1{10-9};
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let Word0{8-0} = src0_sel;
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let Word0{9} = src0_rel;
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let Word0{11-10} = src0_chan;
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let Word0{21-13} = src1_sel;
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let Word0{22} = src1_rel;
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let Word0{24-23} = src1_chan;
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let Word0{28-26} = index_mode;
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let Word0{30-29} = pred_sel;
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let Word0{31} = last;
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}
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class R600ALU_Word0 : R600_ALU_LDS_Word0 {
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bits<1> src0_neg;
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bits<1> src1_neg;
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let Word0{12} = src0_neg;
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let Word0{25} = src1_neg;
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}
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class R600ALU_Word1 {
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field bits<32> Word1;
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bits<11> dst;
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bits<3> bank_swizzle;
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bits<1> dst_rel;
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bits<1> clamp;
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bits<7> dst_sel = dst{6-0};
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bits<2> dst_chan = dst{10-9};
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let Word1{20-18} = bank_swizzle;
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let Word1{27-21} = dst_sel;
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let Word1{28} = dst_rel;
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let Word1{30-29} = dst_chan;
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let Word1{31} = clamp;
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}
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class R600ALU_Word1_OP2 <bits<11> alu_inst> : R600ALU_Word1{
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bits<1> src0_abs;
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bits<1> src1_abs;
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bits<1> update_exec_mask;
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bits<1> update_pred;
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bits<1> write;
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bits<2> omod;
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let Word1{0} = src0_abs;
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let Word1{1} = src1_abs;
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let Word1{2} = update_exec_mask;
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let Word1{3} = update_pred;
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let Word1{4} = write;
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let Word1{6-5} = omod;
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let Word1{17-7} = alu_inst;
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}
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class R600ALU_Word1_OP3 <bits<5> alu_inst> : R600ALU_Word1{
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bits<11> src2;
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bits<1> src2_rel;
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bits<1> src2_neg;
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bits<9> src2_sel = src2{8-0};
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bits<2> src2_chan = src2{10-9};
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let Word1{8-0} = src2_sel;
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let Word1{9} = src2_rel;
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let Word1{11-10} = src2_chan;
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let Word1{12} = src2_neg;
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let Word1{17-13} = alu_inst;
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}
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class R600LDS_Word1 {
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field bits<32> Word1;
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bits<11> src2;
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bits<9> src2_sel = src2{8-0};
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bits<2> src2_chan = src2{10-9};
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bits<1> src2_rel;
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// offset specifies the stride offset to the second set of data to be read
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// from. This is a dword offset.
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bits<5> alu_inst = 17; // OP3_INST_LDS_IDX_OP
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bits<3> bank_swizzle;
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bits<6> lds_op;
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bits<2> dst_chan = 0;
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let Word1{8-0} = src2_sel;
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let Word1{9} = src2_rel;
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let Word1{11-10} = src2_chan;
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let Word1{17-13} = alu_inst;
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let Word1{20-18} = bank_swizzle;
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let Word1{26-21} = lds_op;
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let Word1{30-29} = dst_chan;
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}
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/*
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XXX: R600 subtarget uses a slightly different encoding than the other
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subtargets. We currently handle this in R600MCCodeEmitter, but we may
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want to use these instruction classes in the future.
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class R600ALU_Word1_OP2_r600 : R600ALU_Word1_OP2 {
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bits<1> fog_merge;
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bits<10> alu_inst;
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let Inst{37} = fog_merge;
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let Inst{39-38} = omod;
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let Inst{49-40} = alu_inst;
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}
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class R600ALU_Word1_OP2_r700 : R600ALU_Word1_OP2 {
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bits<11> alu_inst;
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let Inst{38-37} = omod;
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let Inst{49-39} = alu_inst;
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}
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*/
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//===----------------------------------------------------------------------===//
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// Vertex Fetch instructions
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//===----------------------------------------------------------------------===//
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class VTX_WORD0 {
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field bits<32> Word0;
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bits<7> src_gpr;
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bits<5> VC_INST;
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bits<2> FETCH_TYPE;
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bits<1> FETCH_WHOLE_QUAD;
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bits<8> buffer_id;
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bits<1> SRC_REL;
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bits<2> SRC_SEL_X;
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let Word0{4-0} = VC_INST;
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let Word0{6-5} = FETCH_TYPE;
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let Word0{7} = FETCH_WHOLE_QUAD;
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let Word0{15-8} = buffer_id;
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let Word0{22-16} = src_gpr;
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let Word0{23} = SRC_REL;
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let Word0{25-24} = SRC_SEL_X;
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}
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class VTX_WORD0_eg : VTX_WORD0 {
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bits<6> MEGA_FETCH_COUNT;
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let Word0{31-26} = MEGA_FETCH_COUNT;
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}
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class VTX_WORD0_cm : VTX_WORD0 {
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bits<2> SRC_SEL_Y;
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bits<2> STRUCTURED_READ;
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bits<1> LDS_REQ;
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bits<1> COALESCED_READ;
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let Word0{27-26} = SRC_SEL_Y;
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let Word0{29-28} = STRUCTURED_READ;
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let Word0{30} = LDS_REQ;
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let Word0{31} = COALESCED_READ;
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}
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class VTX_WORD1_GPR {
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field bits<32> Word1;
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bits<7> dst_gpr;
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bits<1> DST_REL;
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bits<3> DST_SEL_X;
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bits<3> DST_SEL_Y;
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bits<3> DST_SEL_Z;
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bits<3> DST_SEL_W;
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bits<1> USE_CONST_FIELDS;
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bits<6> DATA_FORMAT;
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bits<2> NUM_FORMAT_ALL;
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bits<1> FORMAT_COMP_ALL;
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bits<1> SRF_MODE_ALL;
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let Word1{6-0} = dst_gpr;
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let Word1{7} = DST_REL;
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let Word1{8} = 0; // Reserved
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let Word1{11-9} = DST_SEL_X;
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let Word1{14-12} = DST_SEL_Y;
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let Word1{17-15} = DST_SEL_Z;
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let Word1{20-18} = DST_SEL_W;
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let Word1{21} = USE_CONST_FIELDS;
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let Word1{27-22} = DATA_FORMAT;
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let Word1{29-28} = NUM_FORMAT_ALL;
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let Word1{30} = FORMAT_COMP_ALL;
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let Word1{31} = SRF_MODE_ALL;
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}
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//===----------------------------------------------------------------------===//
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// Texture fetch instructions
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//===----------------------------------------------------------------------===//
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class TEX_WORD0 {
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field bits<32> Word0;
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bits<5> TEX_INST;
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bits<2> INST_MOD;
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bits<1> FETCH_WHOLE_QUAD;
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bits<8> RESOURCE_ID;
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bits<7> SRC_GPR;
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bits<1> SRC_REL;
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bits<1> ALT_CONST;
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bits<2> RESOURCE_INDEX_MODE;
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bits<2> SAMPLER_INDEX_MODE;
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let Word0{4-0} = TEX_INST;
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let Word0{6-5} = INST_MOD;
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let Word0{7} = FETCH_WHOLE_QUAD;
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let Word0{15-8} = RESOURCE_ID;
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let Word0{22-16} = SRC_GPR;
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let Word0{23} = SRC_REL;
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let Word0{24} = ALT_CONST;
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let Word0{26-25} = RESOURCE_INDEX_MODE;
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let Word0{28-27} = SAMPLER_INDEX_MODE;
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}
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class TEX_WORD1 {
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field bits<32> Word1;
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bits<7> DST_GPR;
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bits<1> DST_REL;
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bits<3> DST_SEL_X;
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bits<3> DST_SEL_Y;
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bits<3> DST_SEL_Z;
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bits<3> DST_SEL_W;
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bits<7> LOD_BIAS;
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bits<1> COORD_TYPE_X;
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bits<1> COORD_TYPE_Y;
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bits<1> COORD_TYPE_Z;
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bits<1> COORD_TYPE_W;
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let Word1{6-0} = DST_GPR;
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let Word1{7} = DST_REL;
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let Word1{11-9} = DST_SEL_X;
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let Word1{14-12} = DST_SEL_Y;
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let Word1{17-15} = DST_SEL_Z;
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let Word1{20-18} = DST_SEL_W;
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let Word1{27-21} = LOD_BIAS;
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let Word1{28} = COORD_TYPE_X;
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let Word1{29} = COORD_TYPE_Y;
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let Word1{30} = COORD_TYPE_Z;
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let Word1{31} = COORD_TYPE_W;
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}
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class TEX_WORD2 {
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field bits<32> Word2;
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bits<5> OFFSET_X;
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bits<5> OFFSET_Y;
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bits<5> OFFSET_Z;
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bits<5> SAMPLER_ID;
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bits<3> SRC_SEL_X;
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bits<3> SRC_SEL_Y;
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bits<3> SRC_SEL_Z;
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bits<3> SRC_SEL_W;
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let Word2{4-0} = OFFSET_X;
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let Word2{9-5} = OFFSET_Y;
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let Word2{14-10} = OFFSET_Z;
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let Word2{19-15} = SAMPLER_ID;
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let Word2{22-20} = SRC_SEL_X;
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let Word2{25-23} = SRC_SEL_Y;
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let Word2{28-26} = SRC_SEL_Z;
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let Word2{31-29} = SRC_SEL_W;
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}
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//===----------------------------------------------------------------------===//
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// Control Flow Instructions
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//===----------------------------------------------------------------------===//
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class CF_WORD1_R600 {
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field bits<32> Word1;
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bits<3> POP_COUNT;
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bits<5> CF_CONST;
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bits<2> COND;
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bits<3> COUNT;
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bits<6> CALL_COUNT;
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bits<1> COUNT_3;
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bits<1> END_OF_PROGRAM;
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bits<1> VALID_PIXEL_MODE;
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bits<7> CF_INST;
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bits<1> WHOLE_QUAD_MODE;
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bits<1> BARRIER;
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let Word1{2-0} = POP_COUNT;
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let Word1{7-3} = CF_CONST;
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let Word1{9-8} = COND;
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let Word1{12-10} = COUNT;
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let Word1{18-13} = CALL_COUNT;
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let Word1{19} = COUNT_3;
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let Word1{21} = END_OF_PROGRAM;
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let Word1{22} = VALID_PIXEL_MODE;
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let Word1{29-23} = CF_INST;
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let Word1{30} = WHOLE_QUAD_MODE;
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let Word1{31} = BARRIER;
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}
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class CF_WORD0_EG {
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field bits<32> Word0;
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bits<24> ADDR;
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bits<3> JUMPTABLE_SEL;
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let Word0{23-0} = ADDR;
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let Word0{26-24} = JUMPTABLE_SEL;
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}
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class CF_WORD1_EG {
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field bits<32> Word1;
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bits<3> POP_COUNT;
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bits<5> CF_CONST;
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bits<2> COND;
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bits<6> COUNT;
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bits<1> VALID_PIXEL_MODE;
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bits<1> END_OF_PROGRAM;
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bits<8> CF_INST;
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bits<1> BARRIER;
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let Word1{2-0} = POP_COUNT;
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let Word1{7-3} = CF_CONST;
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let Word1{9-8} = COND;
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let Word1{15-10} = COUNT;
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let Word1{20} = VALID_PIXEL_MODE;
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let Word1{21} = END_OF_PROGRAM;
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let Word1{29-22} = CF_INST;
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let Word1{31} = BARRIER;
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}
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class CF_ALU_WORD0 {
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field bits<32> Word0;
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bits<22> ADDR;
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bits<4> KCACHE_BANK0;
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bits<4> KCACHE_BANK1;
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bits<2> KCACHE_MODE0;
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let Word0{21-0} = ADDR;
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let Word0{25-22} = KCACHE_BANK0;
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let Word0{29-26} = KCACHE_BANK1;
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let Word0{31-30} = KCACHE_MODE0;
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}
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class CF_ALU_WORD1 {
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field bits<32> Word1;
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bits<2> KCACHE_MODE1;
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bits<8> KCACHE_ADDR0;
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bits<8> KCACHE_ADDR1;
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bits<7> COUNT;
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bits<1> ALT_CONST;
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bits<4> CF_INST;
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bits<1> WHOLE_QUAD_MODE;
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bits<1> BARRIER;
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let Word1{1-0} = KCACHE_MODE1;
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let Word1{9-2} = KCACHE_ADDR0;
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let Word1{17-10} = KCACHE_ADDR1;
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let Word1{24-18} = COUNT;
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let Word1{25} = ALT_CONST;
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let Word1{29-26} = CF_INST;
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let Word1{30} = WHOLE_QUAD_MODE;
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let Word1{31} = BARRIER;
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}
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class CF_ALLOC_EXPORT_WORD0_RAT {
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field bits<32> Word0;
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bits<4> rat_id;
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bits<6> rat_inst;
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bits<2> rim;
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bits<2> type;
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bits<7> rw_gpr;
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bits<1> rw_rel;
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bits<7> index_gpr;
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bits<2> elem_size;
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let Word0{3-0} = rat_id;
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let Word0{9-4} = rat_inst;
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let Word0{10} = 0; // Reserved
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let Word0{12-11} = rim;
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let Word0{14-13} = type;
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let Word0{21-15} = rw_gpr;
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let Word0{22} = rw_rel;
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let Word0{29-23} = index_gpr;
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let Word0{31-30} = elem_size;
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}
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class CF_ALLOC_EXPORT_WORD1_BUF {
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field bits<32> Word1;
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bits<12> array_size;
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bits<4> comp_mask;
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bits<4> burst_count;
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bits<1> vpm;
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bits<1> eop;
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bits<8> cf_inst;
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bits<1> mark;
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bits<1> barrier;
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let Word1{11-0} = array_size;
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let Word1{15-12} = comp_mask;
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let Word1{19-16} = burst_count;
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let Word1{20} = vpm;
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let Word1{21} = eop;
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let Word1{29-22} = cf_inst;
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let Word1{30} = mark;
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let Word1{31} = barrier;
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}
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