Harald van Dijk f675df37ba [X86] Fix handling of maskmovdqu in X32 ... The maskmovdqu instruction is an odd one: it has a 32-bit and a 64-bit variant, the former using EDI, the latter RDI, but the use of the register is implicit. In 64-bit mode, a 0x67 prefix can be used to get the version using EDI, but there is no way to express this in assembly in a single instruction, the only way is with an explicit addr32. This change adds support for the instruction. When generating assembly text, that explicit addr32 will be added. When not generating assembly text, it will be kept as a single instruction and will be emitted with that 0x67 prefix. When parsing assembly text, it will be re-parsed as ADDR32 followed by MASKMOVDQU64, which still results in the correct bytes when converted to machine code. The same applies to vmaskmovdqu as well. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D103427		2021-07-15 22:56:08 +01:00
..
AlignedBundling
AMX
Inputs	[X86] Add test showing binary differences with -x86-pad-for-align.	2021-06-17 12:27:17 +01:00
KEYLOCKER
3DNow.s
2011-09-06-NoNewline.s
abs8.s
addr16-32.s	[X86] Add segment and address-size override prefixes	2021-01-19 23:54:31 -08:00
address-size.s
AES-32.s
AES-64.s
align-branch-32bit.s
align-branch-align.s
align-branch-basic.s
align-branch-boundary-default.s
align-branch-bundle.s
align-branch-enhanced-relaxation.s
align-branch-fused.s
align-branch-general.s
align-branch-hardcode.s
align-branch-mixed.s
align-branch-necessary.s
align-branch-negative.s
align-branch-pad-max-prefix.s
align-branch-prefix.s
align-branch-relax-all.s
align-branch-section-size.s
align-branch-section-type.s
align-branch-single.s
align-branch-system.s
align-branch-variant-symbol.s
align-via-padding-corner.s	[X86] Default to -x86-pad-for-align=false to drop assembler difference with or w/o -g	2021-01-16 16:39:54 -08:00
align-via-padding.s	[X86] Default to -x86-pad-for-align=false to drop assembler difference with or w/o -g	2021-01-16 16:39:54 -08:00
align-via-relaxation.s	[X86] Default to -x86-pad-for-align=false to drop assembler difference with or w/o -g	2021-01-16 16:39:54 -08:00
avx512_bf16_vl-encoding.s
avx512_bf16-encoding.s
avx512-encodings.s
avx512-err.s
avx512bitalg-encoding.s
avx512bw-encoding.s
avx512gfni-encoding.s
avx512ifma-encoding.s
avx512ifmavl-encoding.s
avx512vaes-encoding.s
avx512vbmi2-encoding.s
avx512vbmi2vl-encoding.s
avx512vbmi-encoding.s
avx512vl_bitalg-encoding.s
avx512vl_gfni-encoding.s
avx512vl_vaes-encoding.s
avx512vl_vnni-encoding.s
avx512vl-encoding.s
avx512vlvpclmul.s
avx512vnni-encoding.s
avx512vp2intersectvl-att.s
avx512vp2intersectvl-intel.s
avx512vpclmul.s
avx5124fmaps-encoding.s
avx5124vnniw-encoding.s
AVX2-32.s
AVX2-64.s
AVX512F_512-32.s
AVX512F_512-64.s
AVX512F_SCALAR-32.s
AVX512F_SCALAR-64.s
avx_vaes-encoding.s
avx_vnni-encoding.s	[X86] Support Intel avxvnni	2020-10-31 12:39:51 +08:00
AVX-32.s
AVX-64.s
AVXAES-32.s
AVXAES-64.s
BMI1-32.s
BMI1-64.s
BMI2-32.s
BMI2-64.s
CET-32.s
CET-64.s
cet-encoding.s
cfi_offset-eip.s	[MC][test] Reorganize .cfi_* tests	2020-12-21 17:18:28 -08:00
check-end-of-data-region.s
CLFLUSHOPT-32.s
CLFLUSHOPT-64.s
CLFSH-32.s
CLFSH-64.s
CLWB-32.s
CLWB-64.s
CLZERO-32.s
CLZERO-64.s
code16-32-64.s
code16gcc-align.s	[X86] Use correct padding when in 16-bit mode	2021-02-25 20:05:45 -08:00
code16gcc.s
compact-unwind-cfi_def_cfa.s	[MC][test] Reorganize .cfi_* tests	2020-12-21 17:18:28 -08:00
compact-unwind.s
crlf.test
data-prefix16.s
data-prefix32.s
data-prefix64.s
data-prefix-fail.s
directive-arch.s
disassemble-zeroes.s
dwarf-size-field-overflow.test	[DebugInfo] Bug 41152 - Improve dumping of empty location expressions	2021-06-29 09:21:00 +01:00
encoder-fail.s	[X86] Remove period from end of error message in assembler	2020-10-21 00:43:23 -07:00
error-reloc.s
eval-fill.s
F16C-32.s
F16C-64.s
faultmap-section-parsing.s
fixup-cpu-mode.s
FMA-32.s
FMA-64.s
fp-setup-macho.s
FXSAVE64-64.s
FXSAVE-32.s
FXSAVE-64.s
gather.s
gfni-encoding.s
gnux32-dwarf-gen.s
gotpcrelx.s	[X86] Avoid generating invalid R_X86_64_GOTPCRELX relocations	2020-12-18 23:38:38 +00:00
hex-immediates.s
i386-darwin-frame-register.ll
I86-32.s
I86-64.s
I186-32.s
I186-64.s
I286-32.s
I286-64.s
I386-32.s
I386-64.s
I486-32.s
I486-64.s
imm-comments.s
index-operations.s
inline-asm-obj.ll
intel-syntax-2.s
intel-syntax-32.s
intel-syntax-ambiguous.s
intel-syntax-avx512_bf16_vl.s
intel-syntax-avx512_bf16.s
intel-syntax-avx512-error.s
intel-syntax-avx512.s
intel-syntax-avx_vnni.s	[X86] Support Intel avxvnni	2020-10-31 12:39:51 +08:00
intel-syntax-bitwise-ops.s
intel-syntax-directional-label.s
intel-syntax-encoding.s
intel-syntax-error.s
intel-syntax-hex.s
intel-syntax-invalid-basereg.s
intel-syntax-invalid-scale.s
intel-syntax-print.ll
intel-syntax-ptr-sized.s
intel-syntax-unsized-memory.s
intel-syntax-var-offset.ll	[test] Add explicit dso_local to definitions in ELF static relocation model tests	2020-12-30 15:47:16 -08:00
intel-syntax-x86-64-avx512_bf16_vl.s
intel-syntax-x86-64-avx512_bf16.s
intel-syntax-x86-64-avx512f_vl.s	[X86] Accept 64-bit GPRs for vextractps when using a register that requires EVEX.	2021-02-01 11:01:32 -08:00
intel-syntax-x86-64-avx_vnni.s	[X86] Support Intel avxvnni	2020-10-31 12:39:51 +08:00
intel-syntax-x86-64-avx.s	[X86] Accept 64-bit GPRs for vextractps when using a register that requires EVEX.	2021-02-01 11:01:32 -08:00
intel-syntax-x86-avx512dq_vl.s
intel-syntax-x86-avx512vbmi_vl.s
intel-syntax.s	Fix misspelled instruction in X86 assembly parser	2021-06-13 18:34:15 -04:00
invalid_opcode.s
invalid-sleb.s
INVPCID-32.s
INVPCID-64.s
large-bss.s
line-table-sections.s
lit.local.cfg
LWP-32.s
LWP-64.s
lwp-x86_64.s
lwp.s
macho-reloc-errors-x86_64.s
macho-reloc-errors-x86.s
macho-uleb.s
maskmovdqu64.s	[X86] Fix handling of maskmovdqu in X32	2021-07-15 22:56:08 +01:00
maskmovdqu.s	[X86] Fix handling of maskmovdqu in X32	2021-07-15 22:56:08 +01:00
MMX-32.s
MMX-64.s
mpx-encodings.s
no-elf-compact-unwind.s
pad-for-align-debug.s	[X86] Check using default in test added in 0bd5bbb31e0345ae.	2021-06-17 13:19:43 +01:00
padlock.s
PKU-32.s
PKU-64.s
pltoff.s	[X86] Support modifier @PLTOFF for R_X86_64_PLTOFF64	2020-12-01 08:39:01 -08:00
POPCNT-32.s
POPCNT-64.s
PPRO-32.s
PPRO-64.s
pr22004.s
pr22028.s
pr27884.s
pr28547.s
pr32530.s
pr37425.s
PREFETCH-32.s
PREFETCH-64.s
prefix-padding-32.s	[X86] Default to -x86-pad-for-align=false to drop assembler difference with or w/o -g	2021-01-16 16:39:54 -08:00
prefix-padding-64.s	[X86] Default to -x86-pad-for-align=false to drop assembler difference with or w/o -g	2021-01-16 16:39:54 -08:00
RDPMC-32.s
RDPMC-64.s
RDRAND-32.s
RDRAND-64.s
RDSEED-32.s
RDSEED-64.s
RDTSCP-32.s
RDTSCP-64.s
RDWRFSGS-64.s
relax-insn.s
relax-offset.s
reloc-directive-elf-32.s	[MC][test] Fix reloc-directive-elf-*.s	2021-03-05 21:37:29 -08:00
reloc-directive-elf-64.s	[MC][test] Fix reloc-directive-elf-*.s	2021-03-05 21:37:29 -08:00
reloc-directive.s
reloc-macho.s
reloc-undef-global.s
ret.s
RTM.s
segment-prefix.s	[X86] Add segment and address-size override prefixes	2021-01-19 23:54:31 -08:00
SHA-32.s
SHA-64.s
shuffle-comments.s
signed-coff-pcrel.s
SNP-32.s	[X86] Add TLBSYNC, INVLPGB and SNP instructions	2021-01-08 22:28:53 +05:30
SNP-64.s	[X86] Add TLBSYNC, INVLPGB and SNP instructions	2021-01-08 22:28:53 +05:30
space-err.s
SSE2-32.s
SSE2-64.s
SSE3-32.s
SSE3-64.s
SSE4a-32.s
SSE4a-64.s
SSE41-32.s
SSE41-64.s
SSE42-32.s
SSE42-64.s
SSE_PREFETCH-32.s
SSE_PREFETCH-64.s
SSE-32.s
SSE-64.s
SSEMXCSR-32.s
SSEMXCSR-64.s
SSSE3-32.s
SSSE3-64.s
stackmap-nops.ll
stdcall.s
SVM-32.s	[X86] Teach assembler to accept vmsave/vmload/vmrun/invlpga/skinit with or without the fixed register operands	2020-12-19 11:01:55 -08:00
SVM-64.s	[X86] Teach assembler to accept vmsave/vmload/vmrun/invlpga/skinit with or without the fixed register operands	2020-12-19 11:01:55 -08:00
tlsdesc-32.s
tlsdesc-64.s	[llvm-objdump] Prefix memory operand addresses with '0x'	2021-06-28 14:25:21 +07:00
tlsdesc-x32.s	[llvm-objdump] Prefix memory operand addresses with '0x'	2021-06-28 14:25:21 +07:00
unused_reg_var_assign.s
validate-inst-att.s
validate-inst-intel.s
variant-diagnostics.s
VMFUNC-32.s
VMFUNC-64.s
vpclmulqdq.s
VTX-32.s
VTX-64.s
x86_64-asm-match.s
x86_64-avx-clmul-encoding.s
x86_64-avx-encoding.s
x86_64-bmi-encoding.s
x86_64-directive-nops.s
x86_64-encoding.s
x86_64-fma3-encoding.s
x86_64-fma4-encoding.s
x86_64-hle-encoding.s
x86_64-imm-widths.s
x86_64-rand-encoding.s
x86_64-rtm-encoding.s
x86_64-signed-reloc.s
x86_64-sse4a.s
x86_64-tbm-encoding.s
x86_64-xop-encoding.s
x86_directives.s
x86_errors.s
x86_long_nop.s	[X86] Update tests for znver3	2021-01-07 11:51:50 +05:30
x86_nop.s
x86_operands.s
x86-16.s
x86-32-avx512_vp2intersect-intel.s
x86-32-avx512vp2intersect-att.s
x86-32-avx.s
x86-32-coverage.s	[X86] Add TLBSYNC, INVLPGB and SNP instructions	2021-01-08 22:28:53 +05:30
x86-32-fma3.s
x86-32-ms-inline-asm.s
x86-32.s	[X86] Add TLBSYNC, INVLPGB and SNP instructions	2021-01-08 22:28:53 +05:30
x86-64-avx512_bf16_vl-encoding.s
x86-64-avx512_bf16-encoding.s
x86-64-avx512_vp2intersect-intel.s
x86-64-avx512bw_vl.s
x86-64-avx512bw.s
x86-64-avx512cd_vl.s
x86-64-avx512cd.s
x86-64-avx512dq_vl.s
x86-64-avx512dq.s
x86-64-avx512f_vl.s
x86-64-avx512pf.s
x86-64-avx512vp2intersect-att.s
x86-64-avx512vp2intersectvl-att.s
x86-64-avx512vp2intersectvl-intel.s
x86-64-avx512vpopcntdq.s
x86-64-avx_vnni-encoding.s	[X86] Support Intel avxvnni	2020-10-31 12:39:51 +08:00
x86-64.s	[X86] Add TLBSYNC, INVLPGB and SNP instructions	2021-01-08 22:28:53 +05:30
x86-branch-relaxation.s
x86-directive-nops-errors.s
x86-directive-nops.s
x86-evenDirective.s
x86-GCC-inline-asm-Y-constraints.ll
x86-itanium.ll
x86-jcxz-loop-fixup.s
x86-target-directives.s
x86-windows-itanium-libcalls.ll
X86_64-pku.s
X87-32.s
X87-64.s
XOP-32.s
XOP-64.s
XSAVE-32.s
XSAVE-64.s
XSAVEC-32.s
XSAVEC-64.s
XSAVEOPT-32.s
XSAVEOPT-64.s
XSAVES-32.s
XSAVES-64.s