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5d534d8259
I really needed this, like, factually, yesterday, when verifying dependency breaking idioms for AMD Zen 3 scheduler model. Consider the following example: ``` $ ./bin/llvm-exegesis --mode=inverse_throughput --snippets-file=/tmp/snippet.s --num-repetitions=1000000 --repetition-mode=duplicate Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-4a7e50.o --- mode: inverse_throughput key: instructions: - 'VPXORYrr YMM0 YMM0 YMM0' config: '' register_initial_values: [] cpu_name: znver3 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 1000000 measurements: - { key: inverse_throughput, value: 0.31025, per_snippet_value: 0.31025 } error: '' info: '' assembled_snippet: C5FDEFC0C5FDEFC0C5FDEFC0C5FDEFC0C5FDEFC0C5FDEFC0C5FDEFC0C5FDEFC0C5FDEFC0C5FDEFC0C5FDEFC0C5FDEFC0C5FDEFC0C5FDEFC0C5FDEFC0C5FDEFC0C3 ... ``` What does it tell us? So wait, it can only execute ~3 x86 AVX YMM PXOR zero-idioms per cycle? That doesn't seem right. That's even less than there are pipes supporting this type of op. Now, second example: ``` $ ./bin/llvm-exegesis --mode=inverse_throughput --snippets-file=/tmp/snippet.s --num-repetitions=1000000 --repetition-mode=loop Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-2418b5.o --- mode: inverse_throughput key: instructions: - 'VPXORYrr YMM0 YMM0 YMM0' config: '' register_initial_values: [] cpu_name: znver3 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 1000000 measurements: - { key: inverse_throughput, value: 1.00011, per_snippet_value: 1.00011 } error: '' info: '' assembled_snippet: 49B80800000000000000C5FDEFC0C5FDEFC04983C0FF75F2C3 ... ``` Now that's just worse. Due to the looping, the throughput completely plummeted, and now we can only do a single instruction/cycle!? That's not great. And final example: ``` $ ./bin/llvm-exegesis --mode=inverse_throughput --snippets-file=/tmp/snippet.s --num-repetitions=1000000 --repetition-mode=loop --loop-body-size=1000 Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-c402e2.o --- mode: inverse_throughput key: instructions: - 'VPXORYrr YMM0 YMM0 YMM0' config: '' register_initial_values: [] cpu_name: znver3 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 1000000 measurements: - { key: inverse_throughput, value: 0.167087, per_snippet_value: 0.167087 } error: '' info: '' assembled_snippet: 49B80800000000000000C5FDEFC0C5FDEFC04983C0FF75F2C3 ... ``` So if we merge the previous two approaches, do duplicate this single-instruction snippet 1000x (loop-body-size/instruction count in snippet), and run a loop with 1000 iterations over that duplicated/unrolled snippet, the measured throughput goes through the roof, up to 5.9 instructions/cycle, which finally tells us that this idiom is zero-cycle! Reviewed By: courbet Differential Revision: https://reviews.llvm.org/D102522
134 lines
4.6 KiB
C++
134 lines
4.6 KiB
C++
//===-- SnippetRepetitor.cpp ------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include <array>
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#include <string>
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#include "SnippetRepetitor.h"
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#include "Target.h"
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#include "llvm/ADT/Sequence.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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namespace llvm {
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namespace exegesis {
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namespace {
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class DuplicateSnippetRepetitor : public SnippetRepetitor {
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public:
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using SnippetRepetitor::SnippetRepetitor;
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// Repeats the snippet until there are at least MinInstructions in the
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// resulting code.
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FillFunction Repeat(ArrayRef<MCInst> Instructions, unsigned MinInstructions,
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unsigned LoopBodySize) const override {
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return [Instructions, MinInstructions](FunctionFiller &Filler) {
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auto Entry = Filler.getEntry();
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if (!Instructions.empty()) {
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// Add the whole snippet at least once.
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Entry.addInstructions(Instructions);
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for (unsigned I = Instructions.size(); I < MinInstructions; ++I) {
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Entry.addInstruction(Instructions[I % Instructions.size()]);
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}
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}
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Entry.addReturn();
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};
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}
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BitVector getReservedRegs() const override {
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// We're using no additional registers.
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return State.getRATC().emptyRegisters();
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}
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};
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class LoopSnippetRepetitor : public SnippetRepetitor {
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public:
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explicit LoopSnippetRepetitor(const LLVMState &State)
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: SnippetRepetitor(State),
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LoopCounter(State.getExegesisTarget().getLoopCounterRegister(
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State.getTargetMachine().getTargetTriple())) {}
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// Loop over the snippet ceil(MinInstructions / Instructions.Size()) times.
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FillFunction Repeat(ArrayRef<MCInst> Instructions, unsigned MinInstructions,
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unsigned LoopBodySize) const override {
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return [this, Instructions, MinInstructions,
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LoopBodySize](FunctionFiller &Filler) {
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const auto &ET = State.getExegesisTarget();
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auto Entry = Filler.getEntry();
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auto Loop = Filler.addBasicBlock();
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auto Exit = Filler.addBasicBlock();
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const unsigned LoopUnrollFactor =
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LoopBodySize <= Instructions.size()
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? 1
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: divideCeil(LoopBodySize, Instructions.size());
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assert(LoopUnrollFactor >= 1 && "Should end up with at least 1 snippet.");
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// Set loop counter to the right value:
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const APInt LoopCount(
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32,
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divideCeil(MinInstructions, LoopUnrollFactor * Instructions.size()));
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assert(LoopCount.uge(1) && "Trip count should be at least 1.");
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for (const MCInst &Inst :
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ET.setRegTo(State.getSubtargetInfo(), LoopCounter, LoopCount))
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Entry.addInstruction(Inst);
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// Set up the loop basic block.
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Entry.MBB->addSuccessor(Loop.MBB, BranchProbability::getOne());
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Loop.MBB->addSuccessor(Loop.MBB, BranchProbability::getOne());
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// The live ins are: the loop counter, the registers that were setup by
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// the entry block, and entry block live ins.
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Loop.MBB->addLiveIn(LoopCounter);
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for (unsigned Reg : Filler.getRegistersSetUp())
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Loop.MBB->addLiveIn(Reg);
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for (const auto &LiveIn : Entry.MBB->liveins())
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Loop.MBB->addLiveIn(LiveIn);
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for (auto _ : seq(0U, LoopUnrollFactor)) {
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(void)_;
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Loop.addInstructions(Instructions);
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}
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ET.decrementLoopCounterAndJump(*Loop.MBB, *Loop.MBB,
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State.getInstrInfo());
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// Set up the exit basic block.
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Loop.MBB->addSuccessor(Exit.MBB, BranchProbability::getZero());
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Exit.addReturn();
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};
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}
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BitVector getReservedRegs() const override {
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// We're using a single loop counter, but we have to reserve all aliasing
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// registers.
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return State.getRATC().getRegister(LoopCounter).aliasedBits();
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}
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private:
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const unsigned LoopCounter;
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};
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} // namespace
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SnippetRepetitor::~SnippetRepetitor() {}
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std::unique_ptr<const SnippetRepetitor>
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SnippetRepetitor::Create(InstructionBenchmark::RepetitionModeE Mode,
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const LLVMState &State) {
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switch (Mode) {
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case InstructionBenchmark::Duplicate:
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return std::make_unique<DuplicateSnippetRepetitor>(State);
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case InstructionBenchmark::Loop:
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return std::make_unique<LoopSnippetRepetitor>(State);
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case InstructionBenchmark::AggregateMin:
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break;
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}
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llvm_unreachable("Unknown RepetitionModeE enum");
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}
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} // namespace exegesis
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} // namespace llvm
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