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89 lines
2.4 KiB
C++
89 lines
2.4 KiB
C++
//===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// The file contains the R600 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "R600RegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "R600MachineFunctionInfo.h"
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using namespace llvm;
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R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm,
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const TargetInstrInfo &tii)
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: AMDGPURegisterInfo(tm, tii),
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TM(tm),
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TII(tii)
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{ }
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BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const
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{
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BitVector Reserved(getNumRegs());
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const R600MachineFunctionInfo * MFI = MF.getInfo<R600MachineFunctionInfo>();
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Reserved.set(AMDGPU::ZERO);
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Reserved.set(AMDGPU::HALF);
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Reserved.set(AMDGPU::ONE);
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Reserved.set(AMDGPU::ONE_INT);
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Reserved.set(AMDGPU::NEG_HALF);
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Reserved.set(AMDGPU::NEG_ONE);
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Reserved.set(AMDGPU::PV_X);
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Reserved.set(AMDGPU::ALU_LITERAL_X);
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for (TargetRegisterClass::iterator I = AMDGPU::R600_CReg32RegClass.begin(),
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E = AMDGPU::R600_CReg32RegClass.end(); I != E; ++I) {
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Reserved.set(*I);
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}
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for (std::vector<unsigned>::const_iterator I = MFI->ReservedRegs.begin(),
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E = MFI->ReservedRegs.end(); I != E; ++I) {
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Reserved.set(*I);
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}
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return Reserved;
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}
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const TargetRegisterClass *
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R600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const
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{
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switch (rc->getID()) {
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case AMDGPU::GPRF32RegClassID:
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case AMDGPU::GPRI32RegClassID:
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return &AMDGPU::R600_Reg32RegClass;
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default: return rc;
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}
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}
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unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const
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{
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switch(reg) {
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case AMDGPU::ZERO:
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case AMDGPU::ONE:
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case AMDGPU::ONE_INT:
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case AMDGPU::NEG_ONE:
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case AMDGPU::HALF:
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case AMDGPU::NEG_HALF:
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case AMDGPU::ALU_LITERAL_X:
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return 0;
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default: return getHWRegChanGen(reg);
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}
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}
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const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
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MVT VT) const
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{
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switch(VT.SimpleTy) {
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default:
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case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
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}
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}
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#include "R600HwRegInfo.include"
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