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47 lines
1.7 KiB
TableGen
47 lines
1.7 KiB
TableGen
//=-HexagonScheduleV5.td - HexagonV5 Scheduling Definitions --*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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def LD_tc_ld_SLOT01 : InstrItinClass;
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def ST_tc_st_SLOT01 : InstrItinClass;
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class HexagonV5PseudoItin {
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list<InstrItinData> V5PseudoItin_list = [
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InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [SLOT2, SLOT3]>]>,
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InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>]>,
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InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>]>
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];
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}
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def HexagonV5ItinList : DepScalarItinV5, HexagonV5PseudoItin {
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list<InstrItinData> V5Itin_list = [
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InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>,
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InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>
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];
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list<InstrItinData> ItinList =
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!listconcat(V5Itin_list, DepScalarItinV5_list, V5PseudoItin_list);
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}
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def HexagonItinerariesV5 :
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ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
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[Hex_FWD], HexagonV5ItinList.ItinList>;
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def HexagonModelV5 : SchedMachineModel {
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// Max issue per cycle == bundle width.
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let IssueWidth = 4;
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let Itineraries = HexagonItinerariesV5;
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let LoadLatency = 1;
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let CompleteModel = 0;
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}
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//===----------------------------------------------------------------------===//
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// Hexagon V5 Resource Definitions -
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//===----------------------------------------------------------------------===//
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