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38e5713f51
Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon Reviewed By: RKSimon Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60228 llvm-svn: 357802 |
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| .. | ||
| test_copy_mismatch_types.mir | ||
| test_copy.mir | ||
| test_g_add.mir | ||
| test_g_addrspacecast.mir | ||
| test_g_bitcast.mir | ||
| test_g_build_vector_trunc.mir | ||
| test_g_build_vector.mir | ||
| test_g_concat_vectors.mir | ||
| test_g_constant.mir | ||
| test_g_extract.mir | ||
| test_g_fcmp.mir | ||
| test_g_fconstant.mir | ||
| test_g_gep.mir | ||
| test_g_icmp.mir | ||
| test_g_insert.mir | ||
| test_g_inttoptr.mir | ||
| test_g_load.mir | ||
| test_g_phi.mir | ||
| test_g_ptrtoint.mir | ||
| test_g_select.mir | ||
| test_g_sextload.mir | ||
| test_g_store.mir | ||
| test_g_trunc.mir | ||
| test_g_zextload.mir | ||
| test_phis_precede_nonphis.mir | ||
| verifier-generic-extend-truncate.mir | ||
| verifier-generic-types-1.mir | ||
| verifier-generic-types-2.mir | ||
| verifier-implicit-virtreg-invalid-physreg-liveness.mir | ||
| verifier-phi-fail0.mir | ||
| verifier-phi.mir | ||
| verifier-pseudo-terminators.mir | ||
| verify-regbankselected.mir | ||
| verify-selected.mir | ||