Alex Bradbury e355bee0d9 [RISCV][MC] Modify evaluateConstantImm interface to allow reuse from addExpr ... This is a trivial refactoring that I'm committing now as it makes a patch I'm about to post for review easier to follow. There is some overlap between evaluateConstantImm and addExpr in RISCVAsmParser. This patch allows evaluateConstantImm to be reused from addExpr to remove this overlap. The benefit will be greater when a future patch adds extra code to allows immediates to be evaluated from constant symbols (e.g. `.equ CONST, 0x1234`). No functional change intended. llvm-svn: 342641		2018-09-20 11:40:43 +00:00
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AsmParser	[RISCV][MC] Modify evaluateConstantImm interface to allow reuse from addExpr	2018-09-20 11:40:43 +00:00
Disassembler	[RISCV] Fix decoding of invalid instruction with C extension enabled.	2018-09-13 18:21:19 +00:00
InstPrinter
MCTargetDesc	[Target] Untangle disassemblers	2018-09-10 12:53:46 +00:00
TargetInfo
CMakeLists.txt	[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A	2018-09-19 10:54:22 +00:00
LLVMBuild.txt
RISCV.h	[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A	2018-09-19 10:54:22 +00:00
RISCV.td
RISCVAsmPrinter.cpp
RISCVCallingConv.td
RISCVExpandPseudoInsts.cpp	[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A	2018-09-19 10:54:22 +00:00
RISCVFrameLowering.cpp
RISCVFrameLowering.h
RISCVInstrFormats.td
RISCVInstrFormatsC.td
RISCVInstrInfo.cpp
RISCVInstrInfo.h
RISCVInstrInfo.td	[RISCV][MC] Improve parsing of jal/j operands	2018-09-20 08:10:35 +00:00
RISCVInstrInfoA.td	[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A	2018-09-19 10:54:22 +00:00
RISCVInstrInfoC.td	[RISCV] Fix decoding of invalid instruction with C extension enabled.	2018-09-13 18:21:19 +00:00
RISCVInstrInfoD.td
RISCVInstrInfoF.td	[RISCV] Fix crash in decoding instruction with unknown floating point rounding mode	2018-09-07 18:43:43 +00:00
RISCVInstrInfoM.td
RISCVISelDAGToDAG.cpp
RISCVISelLowering.cpp	[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A	2018-09-19 10:54:22 +00:00
RISCVISelLowering.h	[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A	2018-09-19 10:54:22 +00:00
RISCVMachineFunctionInfo.h
RISCVMCInstLower.cpp
RISCVMergeBaseOffset.cpp
RISCVRegisterInfo.cpp
RISCVRegisterInfo.h
RISCVRegisterInfo.td
RISCVSubtarget.cpp
RISCVSubtarget.h
RISCVTargetMachine.cpp	[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A	2018-09-19 10:54:22 +00:00
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h