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4924de9fcd
This adds new system registers introduced by the Memory Tagging extension. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52488 llvm-svn: 343571
134 lines
3.7 KiB
ArmAsm
134 lines
3.7 KiB
ArmAsm
// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+mte < %s 2>&1| FileCheck %s
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mrs tco
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mrs gcr_el1
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mrs rgsr_el1
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mrs tfsr_el1
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mrs tfsr_el2
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mrs tfsr_el3
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mrs tfsr_el12
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mrs tfsre0_el1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tco
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: gcr_el1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: rgsr_el1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el2
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el3
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el12
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsre0_el1
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mrs tco, #0
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mrs tco, x0
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mrs gcr_el1, x1
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mrs rgsr_el1, x2
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mrs tfsr_el1, x3
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mrs tfsr_el2, x4
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mrs tfsr_el3, x5
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mrs tfsr_el12, x6
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mrs tfsre0_el1, x7
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tco, #0
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tco, x0
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: gcr_el1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: rgsr_el1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el2
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el3
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el12
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsre0_el1
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msr tco
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msr gcr_el1
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msr rgsr_el1
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msr tfsr_el1
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msr tfsr_el2
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msr tfsr_el3
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msr tfsr_el12
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msr tfsre0_el1
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// CHECK: too few operands for instruction
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// CHECK-NEXT: tco
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// CHECK: too few operands for instruction
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// CHECK-NEXT: gcr_el1
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// CHECK: too few operands for instruction
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// CHECK-NEXT: rgsr_el1
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// CHECK: too few operands for instruction
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// CHECK-NEXT: tfsr_el1
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// CHECK: too few operands for instruction
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// CHECK-NEXT: tfsr_el2
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// CHECK: too few operands for instruction
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// CHECK-NEXT: tfsr_el3
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// CHECK: too few operands for instruction
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// CHECK-NEXT: tfsr_el12
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// CHECK: too few operands for instruction
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// CHECK-NEXT: tfsre0_el1
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msr x0, tco
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msr x1, gcr_el1
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msr x2, rgsr_el1
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msr x3, tfsr_el1
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msr x4, tfsr_el2
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msr x5, tfsr_el3
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msr x6, tfsr_el12
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msr x7, tfsre0_el1
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// CHECK: expected writable system register or pstate
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// CHECK-NEXT: tco
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// CHECK: expected writable system register or pstate
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// CHECK-NEXT: gcr_el1
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// CHECK: expected writable system register or pstate
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// CHECK-NEXT: rgsr_el1
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// CHECK: expected writable system register or pstate
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// CHECK-NEXT: tfsr_el1
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// CHECK: expected writable system register or pstate
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// CHECK-NEXT: tfsr_el2
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// CHECK: expected writable system register or pstate
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// CHECK-NEXT: tfsr_el3
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// CHECK: expected writable system register or pstate
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// CHECK-NEXT: tfsr_el12
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// CHECK: expected writable system register or pstate
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// CHECK-NEXT: tfsre0_el1
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// Among the system registers added by MTE, only TCO can be used with MSR (imm).
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// The rest can only be used with MSR (reg).
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msr gcr_el1, #1
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msr rgsr_el1, #2
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msr tfsr_el1, #3
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msr tfsr_el2, #4
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msr tfsr_el3, #5
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msr tfsr_el12, #6
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msr tfsre0_el1, #7
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: gcr_el1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: rgsr_el1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el2
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el3
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsr_el12
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: tfsre0_el1
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