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cb011ec305
PWR9 processor model for instruction scheduling. A subsequent patch will migrate PWR9 to Post RA MIScheduler. https://reviews.llvm.org/D24525 llvm-svn: 290102
469 lines
24 KiB
TableGen
469 lines
24 KiB
TableGen
//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is the top level entry point for the PowerPC target.
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing.
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//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// PowerPC Subtarget features.
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//
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//===----------------------------------------------------------------------===//
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// CPU Directives //
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//===----------------------------------------------------------------------===//
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def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
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def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
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def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
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def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
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def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
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def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
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def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
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def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
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def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
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def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
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def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
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def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
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def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
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"PPC::DIR_E500mc", "">;
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def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
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"PPC::DIR_E5500", "">;
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def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
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def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
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def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
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def DirectivePwr5x
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: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
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def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
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def DirectivePwr6x
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: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
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def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
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def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
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def DirectivePwr9: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR9", "">;
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def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
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"Enable 64-bit instructions">;
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def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",
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"Enable floating-point instructions">;
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def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
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"Enable 64-bit registers usage for ppc32 [beta]">;
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def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
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"Use condition-register bits individually">;
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def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
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"Enable Altivec instructions",
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[FeatureHardFloat]>;
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def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true",
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"Enable SPE instructions",
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[FeatureHardFloat]>;
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def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
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"Enable the MFOCRF instruction">;
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def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
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"Enable the fsqrt instruction",
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[FeatureHardFloat]>;
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def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
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"Enable the fcpsgn instruction",
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[FeatureHardFloat]>;
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def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
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"Enable the fre instruction",
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[FeatureHardFloat]>;
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def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
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"Enable the fres instruction",
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[FeatureHardFloat]>;
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def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
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"Enable the frsqrte instruction",
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[FeatureHardFloat]>;
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def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
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"Enable the frsqrtes instruction",
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[FeatureHardFloat]>;
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def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
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"Assume higher precision reciprocal estimates">;
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def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
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"Enable the stfiwx instruction",
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[FeatureHardFloat]>;
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def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
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"Enable the lfiwax instruction",
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[FeatureHardFloat]>;
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def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
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"Enable the fri[mnpz] instructions",
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[FeatureHardFloat]>;
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def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
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"Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
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[FeatureHardFloat]>;
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def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
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"Enable the isel instruction">;
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def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true",
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"Enable the bpermd instruction">;
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def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true",
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"Enable extended divide instructions">;
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def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
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"Enable the ldbrx instruction">;
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def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true",
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"Enable the cmpb instruction">;
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def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true",
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"Enable icbt instruction">;
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def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
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"Enable Book E instructions",
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[FeatureICBT]>;
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def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
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"Has only the msync instruction instead of sync",
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[FeatureBookE]>;
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def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true",
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"Enable E500/E500mc instructions">;
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def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
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"Enable PPC 4xx instructions">;
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def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
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"Enable PPC 6xx instructions">;
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def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
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"Enable QPX instructions",
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[FeatureHardFloat]>;
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def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
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"Enable VSX instructions",
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[FeatureAltivec]>;
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def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
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"Enable POWER8 Altivec instructions",
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[FeatureAltivec]>;
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def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
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"Enable POWER8 Crypto instructions",
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[FeatureP8Altivec]>;
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def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
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"Enable POWER8 vector instructions",
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[FeatureVSX, FeatureP8Altivec]>;
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def FeatureDirectMove :
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SubtargetFeature<"direct-move", "HasDirectMove", "true",
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"Enable Power8 direct move instructions",
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[FeatureVSX]>;
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def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
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"HasPartwordAtomics", "true",
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"Enable l[bh]arx and st[bh]cx.">;
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def FeatureInvariantFunctionDescriptors :
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SubtargetFeature<"invariant-function-descriptors",
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"HasInvariantFunctionDescriptors", "true",
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"Assume function descriptors are invariant">;
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def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true",
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"Always use indirect calls">;
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def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
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"Enable Hardware Transactional Memory instructions">;
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def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true",
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"Implement mftb using the mfspr instruction">;
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def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true",
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"Target supports add/load integer fusion.">;
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def FeatureFloat128 :
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SubtargetFeature<"float128", "HasFloat128", "true",
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"Enable the __float128 data type for IEEE-754R Binary128.",
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[FeatureVSX]>;
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def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD",
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"POPCNTD_Fast",
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"Enable the popcnt[dw] instructions">;
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// Note that for the a2/a2q processor models we should not use popcnt[dw] by
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// default. These processors do support the instructions, but they're
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// microcoded, and the software emulation is about twice as fast.
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def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD",
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"POPCNTD_Slow",
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"Has slow popcnt[dw] instructions">;
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def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
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"Treat vector data stream cache control instructions as deprecated">;
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def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
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"true",
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"Enable instructions added in ISA 3.0.">;
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def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
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"Enable POWER9 Altivec instructions",
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[FeatureISA3_0, FeatureP8Altivec]>;
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def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
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"Enable POWER9 vector instructions",
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[FeatureISA3_0, FeatureP8Vector,
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FeatureP9Altivec]>;
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// Since new processors generally contain a superset of features of those that
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// came before them, the idea is to make implementations of new processors
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// less error prone and easier to read.
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// Namely:
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// list<SubtargetFeature> Power8FeatureList = ...
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// list<SubtargetFeature> FutureProcessorSpecificFeatureList =
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// [ features that Power8 does not support ]
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// list<SubtargetFeature> FutureProcessorFeatureList =
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// !listconcat(Power8FeatureList, FutureProcessorSpecificFeatureList)
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// Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as
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// well as providing a single point of definition if the feature set will be
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// used elsewhere.
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def ProcessorFeatures {
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list<SubtargetFeature> Power7FeatureList =
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[DirectivePwr7, FeatureAltivec, FeatureVSX,
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FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
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FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
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FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
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FeatureFPRND, FeatureFPCVT, FeatureISEL,
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FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
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Feature64Bit /*, Feature64BitRegs */,
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FeatureBPERMD, FeatureExtDiv,
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FeatureMFTB, DeprecatedDST];
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list<SubtargetFeature> Power8SpecificFeatures =
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[DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto,
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FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic,
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FeatureFusion];
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list<SubtargetFeature> Power8FeatureList =
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!listconcat(Power7FeatureList, Power8SpecificFeatures);
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list<SubtargetFeature> Power9SpecificFeatures =
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[DirectivePwr9, FeatureP9Altivec, FeatureP9Vector, FeatureISA3_0];
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list<SubtargetFeature> Power9FeatureList =
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!listconcat(Power8FeatureList, Power9SpecificFeatures);
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}
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// Note: Future features to add when support is extended to more
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// recent ISA levels:
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//
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// DFP p6, p6x, p7 decimal floating-point instructions
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// POPCNTB p5 through p7 popcntb and related instructions
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//===----------------------------------------------------------------------===//
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// Classes used for relation maps.
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//===----------------------------------------------------------------------===//
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// RecFormRel - Filter class used to relate non-record-form instructions with
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// their record-form variants.
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class RecFormRel;
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// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
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// FMA instruction forms with their corresponding factor-killing forms.
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class AltVSXFMARel {
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bit IsVSXFMAAlt = 0;
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}
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//===----------------------------------------------------------------------===//
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// Relation Map Definitions.
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//===----------------------------------------------------------------------===//
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def getRecordFormOpcode : InstrMapping {
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let FilterClass = "RecFormRel";
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// Instructions with the same BaseName and Interpretation64Bit values
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// form a row.
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let RowFields = ["BaseName", "Interpretation64Bit"];
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// Instructions with the same RC value form a column.
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let ColFields = ["RC"];
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// The key column are the non-record-form instructions.
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let KeyCol = ["0"];
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// Value columns RC=1
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let ValueCols = [["1"]];
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}
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def getNonRecordFormOpcode : InstrMapping {
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let FilterClass = "RecFormRel";
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// Instructions with the same BaseName and Interpretation64Bit values
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// form a row.
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let RowFields = ["BaseName", "Interpretation64Bit"];
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// Instructions with the same RC value form a column.
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let ColFields = ["RC"];
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// The key column are the record-form instructions.
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let KeyCol = ["1"];
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// Value columns are RC=0
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let ValueCols = [["0"]];
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}
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def getAltVSXFMAOpcode : InstrMapping {
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let FilterClass = "AltVSXFMARel";
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// Instructions with the same BaseName and Interpretation64Bit values
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// form a row.
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let RowFields = ["BaseName"];
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// Instructions with the same RC value form a column.
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let ColFields = ["IsVSXFMAAlt"];
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// The key column are the (default) addend-killing instructions.
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let KeyCol = ["0"];
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// Value columns IsVSXFMAAlt=1
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let ValueCols = [["1"]];
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}
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "PPCRegisterInfo.td"
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include "PPCSchedule.td"
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//===----------------------------------------------------------------------===//
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// PowerPC processors supported.
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//
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def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,
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FeatureMFTB]>;
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def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
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FeatureFRES, FeatureFRSQRTE,
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FeatureICBT, FeatureBookE,
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FeatureMSYNC, FeatureMFTB]>;
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def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
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FeatureFRES, FeatureFRSQRTE,
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FeatureICBT, FeatureBookE,
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FeatureMSYNC, FeatureMFTB]>;
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def : Processor<"601", G3Itineraries, [Directive601, FeatureHardFloat]>;
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def : Processor<"602", G3Itineraries, [Directive602, FeatureHardFloat,
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FeatureMFTB]>;
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def : Processor<"603", G3Itineraries, [Directive603,
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FeatureFRES, FeatureFRSQRTE,
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FeatureMFTB]>;
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def : Processor<"603e", G3Itineraries, [Directive603,
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FeatureFRES, FeatureFRSQRTE,
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FeatureMFTB]>;
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def : Processor<"603ev", G3Itineraries, [Directive603,
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FeatureFRES, FeatureFRSQRTE,
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FeatureMFTB]>;
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def : Processor<"604", G3Itineraries, [Directive604,
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FeatureFRES, FeatureFRSQRTE,
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FeatureMFTB]>;
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def : Processor<"604e", G3Itineraries, [Directive604,
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FeatureFRES, FeatureFRSQRTE,
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FeatureMFTB]>;
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def : Processor<"620", G3Itineraries, [Directive620,
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FeatureFRES, FeatureFRSQRTE,
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FeatureMFTB]>;
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def : Processor<"750", G4Itineraries, [Directive750,
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FeatureFRES, FeatureFRSQRTE,
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FeatureMFTB]>;
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def : Processor<"g3", G3Itineraries, [Directive750,
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FeatureFRES, FeatureFRSQRTE,
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FeatureMFTB]>;
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def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
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FeatureFRES, FeatureFRSQRTE,
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FeatureMFTB]>;
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def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
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FeatureFRES, FeatureFRSQRTE,
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FeatureMFTB]>;
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def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
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FeatureFRES, FeatureFRSQRTE,
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FeatureMFTB]>;
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def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
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FeatureFRES, FeatureFRSQRTE,
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FeatureMFTB]>;
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def : ProcessorModel<"970", G5Model,
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[Directive970, FeatureAltivec,
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FeatureMFOCRF, FeatureFSqrt,
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FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
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Feature64Bit /*, Feature64BitRegs */,
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FeatureMFTB]>;
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def : ProcessorModel<"g5", G5Model,
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[Directive970, FeatureAltivec,
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FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
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FeatureFRES, FeatureFRSQRTE,
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Feature64Bit /*, Feature64BitRegs */,
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FeatureMFTB, DeprecatedDST]>;
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def : ProcessorModel<"e500mc", PPCE500mcModel,
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[DirectiveE500mc,
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FeatureSTFIWX, FeatureICBT, FeatureBookE,
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FeatureISEL, FeatureMFTB]>;
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def : ProcessorModel<"e5500", PPCE5500Model,
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[DirectiveE5500, FeatureMFOCRF, Feature64Bit,
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FeatureSTFIWX, FeatureICBT, FeatureBookE,
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FeatureISEL, FeatureMFTB]>;
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def : ProcessorModel<"a2", PPCA2Model,
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[DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
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FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
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FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
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FeatureSTFIWX, FeatureLFIWAX,
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FeatureFPRND, FeatureFPCVT, FeatureISEL,
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FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
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Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>;
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def : ProcessorModel<"a2q", PPCA2Model,
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[DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
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FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
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FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
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FeatureSTFIWX, FeatureLFIWAX,
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FeatureFPRND, FeatureFPCVT, FeatureISEL,
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FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
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Feature64Bit /*, Feature64BitRegs */, FeatureQPX,
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FeatureMFTB]>;
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def : ProcessorModel<"pwr3", G5Model,
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[DirectivePwr3, FeatureAltivec,
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FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
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FeatureSTFIWX, Feature64Bit]>;
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def : ProcessorModel<"pwr4", G5Model,
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[DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
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FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
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FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
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def : ProcessorModel<"pwr5", G5Model,
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[DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
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FeatureFSqrt, FeatureFRE, FeatureFRES,
|
|
FeatureFRSQRTE, FeatureFRSQRTES,
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|
FeatureSTFIWX, Feature64Bit,
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|
FeatureMFTB, DeprecatedDST]>;
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|
def : ProcessorModel<"pwr5x", G5Model,
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|
[DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
|
|
FeatureFSqrt, FeatureFRE, FeatureFRES,
|
|
FeatureFRSQRTE, FeatureFRSQRTES,
|
|
FeatureSTFIWX, FeatureFPRND, Feature64Bit,
|
|
FeatureMFTB, DeprecatedDST]>;
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|
def : ProcessorModel<"pwr6", G5Model,
|
|
[DirectivePwr6, FeatureAltivec,
|
|
FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
|
|
FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
|
|
FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
|
|
FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
|
|
FeatureMFTB, DeprecatedDST]>;
|
|
def : ProcessorModel<"pwr6x", G5Model,
|
|
[DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
|
|
FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
|
|
FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
|
|
FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
|
|
FeatureFPRND, Feature64Bit,
|
|
FeatureMFTB, DeprecatedDST]>;
|
|
def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>;
|
|
def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
|
|
def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.Power9FeatureList>;
|
|
def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
|
|
FeatureMFTB]>;
|
|
def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
|
|
FeatureMFTB]>;
|
|
def : ProcessorModel<"ppc64", G5Model,
|
|
[Directive64, FeatureAltivec,
|
|
FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
|
|
FeatureFRSQRTE, FeatureSTFIWX,
|
|
Feature64Bit /*, Feature64BitRegs */,
|
|
FeatureMFTB]>;
|
|
def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Calling Conventions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "PPCCallingConv.td"
|
|
|
|
def PPCInstrInfo : InstrInfo {
|
|
let isLittleEndianEncoding = 1;
|
|
|
|
// FIXME: Unset this when no longer needed!
|
|
let decodePositionallyEncodedOperands = 1;
|
|
|
|
let noNamedPositionallyEncodedOperands = 1;
|
|
}
|
|
|
|
def PPCAsmParser : AsmParser {
|
|
let ShouldEmitMatchRegisterName = 0;
|
|
}
|
|
|
|
def PPCAsmParserVariant : AsmParserVariant {
|
|
int Variant = 0;
|
|
|
|
// We do not use hard coded registers in asm strings. However, some
|
|
// InstAlias definitions use immediate literals. Set RegisterPrefix
|
|
// so that those are not misinterpreted as registers.
|
|
string RegisterPrefix = "%";
|
|
string BreakCharacters = ".";
|
|
}
|
|
|
|
def PPC : Target {
|
|
// Information about the instructions.
|
|
let InstructionSet = PPCInstrInfo;
|
|
|
|
let AssemblyParsers = [PPCAsmParser];
|
|
let AssemblyParserVariants = [PPCAsmParserVariant];
|
|
}
|