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443 lines
14 KiB
Plaintext
443 lines
14 KiB
Plaintext
Content:
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========
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. Remaining Instructions (Total 56 Instructions, include 2 unknow instructions)
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. Done (Total 155 Instructions: 101 VSX, 54 Altivec)
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//------------------------------------------------------------------------------
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//. Remaining Instructions
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//------------------------------------------------------------------------------
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GCC reference: https://sourceware.org/ml/binutils/2015-11/msg00071.html
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// Add PC Immediate Shifted DX-form p69
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[PO RT d1 d0 XO d2] addpcis RT,D
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subpcis Rx,value = addpcis Rx,-value
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// 6.17.2 Decimal Integer Format Conversion Instructions
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// Decimal Convert From National VX-form p352
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[PO VRT EO VRB 1 PS XO] bcdcfn. VRT,VRB,PS
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// Decimal Convert From Zoned VX-form p353
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[PO VRT EO VRB 1 PS XO] bcdcfz. VRT,VRB,PS
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// Decimal Convert To National VX-form p354
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[PO VRT EO VRB 1 / XO] bcdctn. VRT,VRB
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// Decimal Convert To Zoned VX-form p355
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[PO VRT EO VRB 1 PS XO] bcdctz. VRT,VRB,PS
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// Decimal Convert From Signed Quadword VX-form p356
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[PO VRT EO VRB 1 PS XO] bcdcfsq. VRT,VRB,PS
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// Decimal Convert To Signed Quadword VX-form p356
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[PO VRT EO VRB 1 / XO] bcdctsq. VRT,VRB
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// 6.17.3 Decimal Integer Sign Manipulation Instructions
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// Decimal Copy Sign VX-form p358
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[PO VRT VRA VRB XO] bcdcpsgn. VRT,VRA,VRB
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// Decimal Set Sign VX-form p358
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[PO VRT EO VRB 1 PS XO] bcdsetsgn. VRT,VRB,PS
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// Decimal Shift VX-form p359
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[PO VRT VRA VRB 1 PS XO] bcds. VRT,VRA,VRB,PS
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// Decimal Unsigned Shift VX-form p360
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[PO VRT VRA VRB 1 / XO] bcdus. VRT,VRA,VRB
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// Decimal Shift and Round VX-form p361
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[PO VRT VRA VRB 1 PS XO] bcdsr. VRT,VRA,VRB,PS
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// 6.17.5 Decimal Integer Truncate Instructions
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// Decimal Truncate VX-form p362
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[PO VRT VRA VRB 1 PS XO] bcdtrunc. VRT,VRA,VRB,PS
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// Decimal Unsigned Truncate VX-form p363
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[PO VRT VRA VRB 1 / XO] bcdutrunc. VRT,VRA,VRB
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// 3.3.10.1 Character-Type Compare Instructions
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// Compare Ranged Byte X-form p87
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[PO BF / L RA RB XO /] cmprb BF,L,RA,RB
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// Compare Equal Byte X-form p88
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[PO BF // RA RB XO /] cmpeqb BF,RA,RB
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// 3.3.13 Fixed-Point Logical Instructions
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// Count Trailing Zeros Word X-form p95
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[PO RS RA /// XO Rc] cnttzw(.) RA,RS
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// 3.3.13.1 64-bit Fixed-Point Logical Instructions
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// Count Trailing Zeros Doubleword X-form p98
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[PO RS RA /// XO Rc] cnttzd(.) RA,RS
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// 4.4 Copy-Paste Facility
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// Copy X-form p858
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[PO /// L RA RB XO /] copy RA,RB,L
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copy_first = copy RA, RB, 1
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// CP_Abort p860
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[PO /// /// /// XO /] cp_abort
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// Paste p859
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[PO /// L RA RB XO Rc] paste(.) RA,RB,L
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paste_last = paste RA,RB,1
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// 3.3.9 Fixed-Point Arithmetic Instructions
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// Deliver A Random Number X-form p79
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[PO RT /// L /// XO /] darn RT,L
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// Multiply-Add High Doubleword VA-form p81
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[PO RT RA RB RC XO] maddhd RT,RA.RB,RC
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// Multiply-Add High Doubleword Unsigned VA-form p81
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[PO RT RA RB RC XO] maddhdu RT,RA.RB,RC
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// Multiply-Add Low Doubleword VA-form p81
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[PO RT RA RB RC XO] maddld RT,RA.RB,RC
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// Modulo Signed Word X-form p76
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[PO RT RA RB XO /] modsw RT,RA,RB
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// Modulo Unsigned Word X-form p76
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[PO RT RA RB XO /] moduw RT,RA,RB
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// Modulo Signed Doubleword X-form p84
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[PO RT RA RB XO /] modsd RT,RA,RB
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// Modulo Unsigned Doubleword X-form p84
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[PO RT RA RB XO /] modud RT,RA,RB
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// DFP Test Significance Immediate [Quad] X-form p204
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[PO BF / UIM FRB XO /] dtstsfi BF,UIM,FRB
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[PO BF / UIM FRBp XO /] dtstsfiq BF,UIM,FRBp
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// 3.3.14.2.1 64-bit Fixed-Point Shift Instructions
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// Extend-Sign Word and Shift Left Immediate XS-form p109
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[PO RS RA sh XO sh Rc] extswsli(.) RA,RS,SH
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// 4.5.1 Load Atomic
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// Load Word Atomic X-form p864
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[PO RT RA FC XO /] lwat RT,RA,FC
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// Load Doubleword Atomic X-form p864
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[PO RT RA FC XO /] ldat RT,RA,FC
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// 4.5.2 Store Atomic
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// Store Word Atomic X-form p866
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[PO RS RA FC XO /] stwat RS,RA,FC
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// Store Doubleword Atomic X-form p866
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[PO RS RA FC XO /] stdat RS,RA,FC
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// 3.3.2.1 64-bit Fixed-Point Load Instructions
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// Load Doubleword Monitored Indexed X-form p54
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[PO RT RA RB XO /] ldmx RT,RA,RB
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// 3.3.16 Move To/From Vector-Scalar Register Instructions
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// Move From VSR Lower Doubleword XX1-form p111
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[PO S RA /// XO SX] mfvsrld RA,XS
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// Move To VSR Double Doubleword XX1-form p114
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[PO T RA RB XO TX] mtvsrdd XT,RA,RB
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// Move To VSR Word & Splat XX1-form p115
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[PO T RA /// XO TX] mtvsrws XT,RA
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// Move to CR from XER Extended X-form p119
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[PO BF // /// /// XO /] mcrxrx BF
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// Set Boolean X-form p121
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[PO RT BFA // /// XO /] setb RT,BFA
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// Message Synchronize X-form p1126
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[PO /// /// /// XO /] msgsync
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// SLB Invalidate Entry Global X-form p1026
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[PO RS /// RB XO /] slbieg RS,RB
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// SLB Synchronize X-form p1031
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[PO /// /// /// XO /] slbsync
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// 3.3.2.1 Power-Saving Mode Instruction
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// stop XL-form p957
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[PO /// /// /// XO /] stop
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// 4.6.4 Wait Instruction
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// Wait X-form p880
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[PO /// WC /// /// XO /] wait
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// Unknow Instructions:
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urfid
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- gcc's implementation:
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{"urfid", XL(19,306), 0xffffffff, POWER9, PPCNONE, {0}},
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(4c 00 02 64|64 02 00 4c) urfid
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rmieg
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- gcc's implementation:
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{"rmieg", X(31,882), XRTRA_MASK, POWER9, PPCNONE, {RB}},
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(7c 00 f6 e4|e4 f6 00 7c) rmieg r30
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//------------------------------------------------------------------------------
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//. Done:
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//------------------------------------------------------------------------------
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//======================================
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"vsx instructions"
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//--------------------------------------
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"7.6.1.2.1 VSX Scalar Move Instructions"
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// VSX Scalar Quad-Precision Move Instructions
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// VSX Scalar Copy Sign Quad-Precision X-form p.553
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[PO VRT VRA VRB XO /] xscpsgnqp
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// VSX Scalar Absolute Quad-Precision X-form 531
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// VSX Scalar Negate Quad-Precision X-form 627
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// VSX Scalar Negative Absolute Quad-Precision X-form 626
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[PO VRT XO VRB XO /] xsabsqp xsnegqp xsnabsqp
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//--------------------------------------
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"7.6.1.3 VSX Floating-Point Arithmetic Instructions"
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// VSX Scalar Quad-Precision Elementary Arithmetic
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// VSX Scalar Add Quad-Precision [using round to Odd] X-form 539
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// VSX Scalar Divide Quad-Precision [using round to Odd] X-form 584
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// VSX Scalar Multiply Quad-Precision [using round to Odd] X-form 622
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[PO VRT VRA VRB XO RO] xsaddqp xsaddqpo xsdivqp xsdivqpo xsmulqp xsmulqpo
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// VSX Scalar Square Root Quad-Precision [using round to Odd] X-form 662
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// VSX Scalar Subtract Quad-Precision [using round to Odd] X-form 667
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xssubqp xssubqpo
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[PO VRT XO VRB XO RO] xssqrtqp xssqrtqpo
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// VSX Scalar Quad-Precision Multiply-Add Arithmetic Instructions
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// VSX Scalar Multiply-Add Quad-Precision [using round to Odd] X-form 596
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// VSX Scalar Multiply-Subtract Quad-Precision [using round to Odd] X-form 617
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// VSX Scalar Negative Multiply-Add Quad-Precision [using round to Odd] X-form 636
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// VSX Scalar Negative Multiply-Subtract Quad-Precision [using round to Odd]
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// X-form 645
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[PO VRT VRA VRB XO RO] xsmaddqp xsmaddqpo xsmsubqp xsmsubqpo
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xsnmaddqp xsnmaddqpo xsnmsubqp xsnmsubqpo
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22
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//--------------------------------------
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"7.6.1.4 VSX Floating-Point Compare Instructions"
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// VSX Scalar Quad-Precision Compare Instructions
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// VSX Scalar Compare Ordered Quad-Precision X-form 549
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// VSX Scalar Compare Unordered Quad-Precision X-form 552
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[PO BF // VRA VRB XO /] xscmpoqp xscmpuqp
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"7.6.1.8 VSX Scalar Floating-Point Support Instructions"
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// VSX Scalar Compare Exponents Quad-Precision X-form p. 541 542
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[PO BF // A B XO AX BX /] xscmpexpdp
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[PO BF // VRA VRB XO /] xscmpexpqp
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// VSX Scalar Compare DP, XX3-form, p.543 544 545
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// VSX Scalar Compare Equal Double-Precision,
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[PO T A B XO AX BX TX] xscmpeqdp xscmpgedp xscmpgtdp xscmpnedp
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// VSX Vector Compare Not Equal Double-Precision XX3-form 691
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[PO T A B Rc XO AX BX TX] xvcmpnedp xvcmpnedp. xvcmpnesp xvcmpnesp.
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//--------------------------------------
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"7.6.1.5 VSX FP-FP Conversion Instructions"
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// VSX Scalar Quad-Precision Floating-Point Conversion Instructions
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// VSX Scalar round & Convert Quad-Precision format to Double-Precision format
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// [using round to Odd] X-form 567
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[PO VRT XO VRB XO /] xscvqpdp xscvqpdpo (actually [PO VRT XO VRB XO RO])
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[PO VRT XO VRB XO /] xscvdpqp
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// VSX Scalar Quad-Precision Convert to Integer Instructions
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// VSX Scalar truncate & Convert Quad-Precision format to Signed Doubleword format
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// 568 570 572 574
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[PO VRT XO VRB XO /] xscvqpsdz xscvqpswz xscvqpudz xscvqpuwz
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576 = 580 xscvsdqp xscvudqp
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"7.6.1.7 VSX Round to Floating-Point Integer Instructions"
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// VSX Scalar round & Convert Double-Precision format to Half-Precision format
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// XX2-form 554 566
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[PO T XO B XO BX TX] xscvdphp xscvhpdp
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// VSX Vector Convert Half-Precision format to Single-Precision format
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// XX2-form 703 705
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[PO T XO B XO BX TX] xvcvhpsp xvcvsphp
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// VSX Scalar Round to Quad-Precision Integer [with Inexact] Z23-form 654
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[PO VRT /// R VRB RMC XO EX] xsrqpi xsrqpix
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// VSX Scalar Round Quad-Precision to Double-Extended Precision Z23-form 656
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[PO VRT /// R VRB RMC XO /] xsrqpxp
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def XSRQPXP : Z23Form_1<63, 37,
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(outs vrrc:$vT), (ins u5imm:$R, vrrc:$vB, u2imm:$RMC),
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"xsrqpxp $vT, $R, $vB, $RMC"), IIC_VecFP, []>;
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27~28
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//--------------------------------------
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// VSX Scalar Insert Exponent Double-Precision X-form 588
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// VSX Scalar Insert Exponent Quad-Precision X-form 589
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[PO VT rA rB XO /] xsiexpdp
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[PO VRT VRA VRB XO /] xsiexpqp
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// VSX Vector Insert Exponent Double-Precision XX3-form 722
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[PO T A B XO AX BX TX] xviexpdp xviexpsp
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// VSX Vector Extract Unsigned Word XX2-form 788
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// VSX Vector Insert Word XX2-form
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[PO T / UIM B XO BX TX] xxextractuw xxinsertw
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// VSX Scalar Extract Exponent Double-Precision XX2-form 676
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[PO BF DCMX B XO BX /]
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[PO T XO B XO BX /] xsxexpdp xsxsigdp
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// X-form
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[PO VRT XO VRB XO /] xsxexpqp xsxsigqp
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// VSX Vector Extract Exponent Double-Precision XX2-form 784
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[PO T XO B XO BX TX] xvxexpdp xvxexpsp
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// VSX Vector Extract Significand Double-Precision XX2-form 785
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[PO T XO B XO BX TX] xvxsigdp xvxsigsp
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//--------------------------------------
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// VSX Scalar Test Data Class Double-Precision XX2-form p673
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// VSX Scalar Test Data Class Quad-Precision X-form 674
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// VSX Scalar Test Data Class Single-Precision XX2-form 675
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[PO BF DCMX B XO BX /] xststdcdp xststdcsp
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[PO BF DCMX VRB XO /] xststdcqp
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// VSX Vector Test Data Class Double-Precision XX2-form 782 783
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[PO T dx B XO dc XO dm BX TX] xvtstdcdp xvtstdcsp
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//--------------------------------------
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// VSX Scalar Maximum Type-C Double-Precision XX3-form 601 ~ 609
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[PO T A B XO AX BX TX] xsmaxcdp xsmaxjdp xsmincdp xsminjdp
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//--------------------------------------
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// VSX Vector Byte-Reverse Doubleword XX2-form 786 787
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[PO T XO B XO BX TX] xxbrd xxbrh xxbrq xxbrw
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// VSX Vector Permute XX3-form 794
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[PO T A B XO AX BX TX] xxperm xxpermr
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// VSX Vector Splat Immediate Byte 796 x-form
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[PO T EO IMM8 XO TX] xxspltib <= sign or unsigned?
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30
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//--------------------------------------
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// Load VSX Vector DQ-form 511
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[PO T RA DQ TX XO] lxv
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// Store VSX Vector DQ-form 526
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[PO S RA DQ SX XO] stxv
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// Load VSX Scalar Doubleword DS-form 499
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// Load VSX Scalar Single DS-form 504
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[PO VRT RA DS XO] lxsd lxssp
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// Store VSX Scalar Doubleword DS-form 517
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// Store VSX Scalar Single DS-form 520
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[PO VRT RA DS XO] stxsd stxssp
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// Load VSX Vector Indexed X-form 511
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// Load VSX Scalar as Integer Byte & Zero Indexed X-form 501
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// Load VSX Vector Byte*16 Indexed X-form 506
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// Load VSX Vector with Length X-form 508
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// Load VSX Vector Left-justified with Length X-form 510
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// Load VSX Vector Halfword*8 Indexed X-form 514
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// Load VSX Vector Word & Splat Indexed X-form 516
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[PO T RA RB XO TX] lxvx lxsibzx lxsihzx lxvb16x lxvl lxvll lxvh8x lxvwsx
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// Store VSX Scalar as Integer Byte Indexed X-form 518
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// Store VSX Scalar as Integer Halfword Indexed X-form 518
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// Store VSX Vector Byte*16 Indexed X-form 522
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// Store VSX Vector Halfword*8 Indexed X-form 524
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// Store VSX Vector with Length X-form 526
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// Store VSX Vector Left-justified with Length X-form 528
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// Store VSX Vector Indexed X-form 529
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[PO S RA RB XO SX] stxsibx stxsihx stxvb16x stxvh8x stxvl stxvll stxvx
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21
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//--------------------------------------
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". vector instructions"
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[1] PowerISA-v3.0 p.933 - Table 1, and Chapter 6. Vector Facility (altivec)
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[2] https://sourceware.org/ml/binutils/2015-11/msg00071.html
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//--------------------------------------
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New patch:
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// vector bit, p.367, 6.16 Vector Bit Permute Instruction
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[PO VRT VRA VRB XO] vbpermd, (existing: vbpermq)
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// vector permute, p.280
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[PO VRT VRA VRB VRC XO] vpermr
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// vector rotate left, p.341
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[PO VRT VRA VRB XO] vrlwnm vrlwmi vrldnm vrldmi
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// vector shift, p.285
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[PO VRT VRA VRB XO] vslv vsrv
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// vector multiply-by-10, p.375
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[PO VRT VRA /// XO] vmul10cuq vmul10uq
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[PO VRT VRA VRB XO] vmul10ecuq vmul10euq
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12
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//--------------------------------------
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http://reviews.llvm.org/D15887 + ext + neg + prty - vbpermd
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// vector count leading/trailing zero
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. new vx-form: p.31, 1.6.14 VX-FORM
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[PO RT EO VRB XO] vclzlsbb vctzlsbb (p.363)
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// Vector Count Trailing Zeros Instructions, 362
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[PO VRT EO VRB XO] vctzb vctzh vctzw vctzd (v16i8 v8i16 v4i32 v2i64)
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// vector extend sign (p.314)
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[PO VRT EO VRB XO] vextsb2w vextsh2w vextsb2d vextsh2d vextsw2d
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// vector negate, p.313
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[PO VRT EO VRB XO] vnegd vnegw
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// vector parity, p.335
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[PO VRT EO VRB XO] vprtybd vprtybq vprtybw
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16
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//--------------------------------------
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// vector compare, p.330
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[PO VRT VRA VRB RC XO] vcmpneb vcmpneb. vcmpneh vcmpneh. vcmpnew vcmpnew.
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vcmpnezb vcmpnezb. vcmpnezh vcmpnezh. vcmpnezw vcmpnezw.
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12
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//--------------------------------------
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http://reviews.llvm.org/D15917 + insert
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// vector extract (p.287) ref: vspltb (v2.07, p.227)
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// vector insert, p.288
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[PO VRT / UIM VRB XO] vinsertb vinsertd vinserth vinsertw
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// Vector Extract Unsigned
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[PO VRT / UIM VRB XO] vextractub vextractuh vextractuw vextractd
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// p.364: Vector Extract Unsigned Left/Right-Indexed
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[PO RT RA VRB XO] vextublx vextubrx vextuhlx vextuhrx vextuwlx vextuwrx
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14
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