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cb25653e71
This patch addresses the inherent big-endian bias in the lxvd2x, lxvw4x, stxvd2x, and stxvw4x instructions. These instructions load vector elements into registers left-to-right (with the first element loaded into the high-order bits of the register), regardless of the endian setting of the processor. However, these are the only vector memory instructions that permit unaligned storage accesses, so we want to use them for little-endian. To make this work, a lxvd2x or lxvw4x is replaced with an lxvd2x followed by an xxswapd, which swaps the doublewords. This works for lxvw4x as well as lxvd2x, because for lxvw4x on an LE system the vector elements are in LE order (right-to-left) within each doubleword. (Thus after lxvw2x of a <4 x float> the elements will appear as 1, 0, 3, 2. Following the swap, they will appear as 3, 2, 0, 1, as desired.) For stores, an stxvd2x or stxvw4x is replaced with an stxvd2x preceded by an xxswapd. Introduction of extra swap instructions provides correctness, but obviously is not ideal from a performance perspective. Future patches will address this with optimizations to remove most of the introduced swaps, which have proven effective in other implementations. The introduction of the swaps is performed during lowering of LOAD, STORE, INTRINSIC_W_CHAIN, and INTRINSIC_VOID operations. The latter are used to translate intrinsics that specify the VSX loads and stores directly into equivalent sequences for little endian. Thus code that uses vec_vsx_ld and vec_vsx_st does not have to be modified to be ported from BE to LE. We introduce new PPCISD opcodes for LXVD2X, STXVD2X, and XXSWAPD for use during this lowering step. In PPCInstrVSX.td, we add new SDType and SDNode definitions for these (PPClxvd2x, PPCstxvd2x, PPCxxswapd). These are recognized during instruction selection and mapped to the correct instructions. Several tests that were written to use -mcpu=pwr7 or pwr8 are modified to disable VSX on LE variants because code generation changes with this and subsequent patches in this set. I chose to include all of these in the first patch than try to rigorously sort out which tests were broken by one or another of the patches. Sorry about that. The new test vsx-ldst-builtin-le.ll, and the changes to vsx-ldst.ll, are disabled until LE support is enabled because of breakages that occur as noted in those tests. They are re-enabled in patch 4/4. llvm-svn: 223783
155 lines
3.4 KiB
LLVM
155 lines
3.4 KiB
LLVM
; RUN: llc -mcpu=pwr7 -mattr=+altivec -mattr=-vsx < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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@g = common global ppc_fp128 0xM00000000000000000000000000000000, align 16
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define void @callee(ppc_fp128 %x) {
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entry:
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%x.addr = alloca ppc_fp128, align 16
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store ppc_fp128 %x, ppc_fp128* %x.addr, align 16
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%0 = load ppc_fp128* %x.addr, align 16
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store ppc_fp128 %0, ppc_fp128* @g, align 16
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ret void
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}
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; CHECK: @callee
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; CHECK: ld [[REG:[0-9]+]], .LC
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; CHECK: stfd 2, 8([[REG]])
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; CHECK: stfd 1, 0([[REG]])
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; CHECK: blr
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define void @caller() {
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entry:
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%0 = load ppc_fp128* @g, align 16
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call void @test(ppc_fp128 %0)
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ret void
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}
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; CHECK: @caller
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; CHECK: ld [[REG:[0-9]+]], .LC
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; CHECK: lfd 2, 8([[REG]])
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; CHECK: lfd 1, 0([[REG]])
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; CHECK: bl test
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declare void @test(ppc_fp128)
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define void @caller_const() {
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entry:
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call void @test(ppc_fp128 0xM3FF00000000000000000000000000000)
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ret void
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}
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; CHECK: .LCPI[[LC:[0-9]+]]_0:
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; CHECK: .long 1065353216
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; CHECK: .LCPI[[LC]]_1:
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; CHECK: .long 0
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; CHECK: @caller_const
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; CHECK: addi [[REG0:[0-9]+]], {{[0-9]+}}, .LCPI[[LC]]_0
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; CHECK: addi [[REG1:[0-9]+]], {{[0-9]+}}, .LCPI[[LC]]_1
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; CHECK: lfs 1, 0([[REG0]])
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; CHECK: lfs 2, 0([[REG1]])
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; CHECK: bl test
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define ppc_fp128 @result() {
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entry:
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%0 = load ppc_fp128* @g, align 16
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ret ppc_fp128 %0
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}
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; CHECK: @result
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; CHECK: ld [[REG:[0-9]+]], .LC
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; CHECK: lfd 1, 0([[REG]])
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; CHECK: lfd 2, 8([[REG]])
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; CHECK: blr
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define void @use_result() {
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entry:
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%call = tail call ppc_fp128 @test_result() #3
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store ppc_fp128 %call, ppc_fp128* @g, align 16
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ret void
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}
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; CHECK: @use_result
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; CHECK: bl test_result
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; CHECK: ld [[REG:[0-9]+]], .LC
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; CHECK: stfd 2, 8([[REG]])
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; CHECK: stfd 1, 0([[REG]])
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; CHECK: blr
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declare ppc_fp128 @test_result()
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define void @caller_result() {
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entry:
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%call = tail call ppc_fp128 @test_result()
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tail call void @test(ppc_fp128 %call)
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ret void
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}
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; CHECK: @caller_result
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; CHECK: bl test_result
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl test
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; CHECK-NEXT: nop
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define i128 @convert_from(ppc_fp128 %x) {
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entry:
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%0 = bitcast ppc_fp128 %x to i128
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ret i128 %0
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}
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; CHECK: @convert_from
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; CHECK: stfd 1, [[OFF1:.*]](1)
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; CHECK: stfd 2, [[OFF2:.*]](1)
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; CHECK: ld 3, [[OFF1]](1)
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; CHECK: ld 4, [[OFF2]](1)
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; CHECK: blr
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define ppc_fp128 @convert_to(i128 %x) {
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entry:
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%0 = bitcast i128 %x to ppc_fp128
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ret ppc_fp128 %0
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}
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; CHECK: @convert_to
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; CHECK: std 3, [[OFF1:.*]](1)
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; CHECK: std 4, [[OFF2:.*]](1)
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; CHECK: lfd 1, [[OFF1]](1)
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; CHECK: lfd 2, [[OFF2]](1)
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; CHECK: blr
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define ppc_fp128 @convert_to2(i128 %x) {
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entry:
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%shl = shl i128 %x, 1
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%0 = bitcast i128 %shl to ppc_fp128
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ret ppc_fp128 %0
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}
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; CHECK: @convert_to
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; CHECK: std 3, [[OFF1:.*]](1)
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; CHECK: std 4, [[OFF2:.*]](1)
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; CHECK: lfd 1, [[OFF1]](1)
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; CHECK: lfd 2, [[OFF2]](1)
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; CHECK: blr
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define double @convert_vector(<4 x i32> %x) {
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entry:
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%cast = bitcast <4 x i32> %x to ppc_fp128
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%conv = fptrunc ppc_fp128 %cast to double
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ret double %conv
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}
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; CHECK: @convert_vector
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; CHECK: addi [[REG:[0-9]+]], 1, [[OFF:.*]]
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; CHECK: stvx 2, 0, [[REG]]
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; CHECK: lfd 1, [[OFF]](1)
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; CHECK: blr
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declare void @llvm.va_start(i8*)
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define double @vararg(i32 %a, ...) {
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entry:
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%va = alloca i8*, align 8
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%va1 = bitcast i8** %va to i8*
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call void @llvm.va_start(i8* %va1)
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%arg = va_arg i8** %va, ppc_fp128
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%conv = fptrunc ppc_fp128 %arg to double
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ret double %conv
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}
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; CHECK: @vararg
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; CHECK: lfd 1, 0({{[0-9]+}})
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; CHECK: blr
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