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49a12f79c1
LDtocL, and other loads that roughly correspond to the TOC_ENTRY SDAG node, represent loads from the TOC, which is invariant. As a result, these loads can be hoisted out of loops, etc. In order to do this, we need to generate GOT-style MMOs for TOC_ENTRY, which requires treating it as a legitimate memory intrinsic node type. Once this is done, the MMO transfer is automatically handled for TableGen-driven instruction selection, and for nodes generated directly in PPCISelDAGToDAG, we need to transfer the MMOs manually. Also, we were not transferring MMOs associated with pre-increment loads, so do that too. Lastly, this fixes an exposed bug where R30 was not added as a defined operand of UpdateGBR. This problem was highlighted by an example (used to generate the test case) posted to llvmdev by Francois Pichet. llvm-svn: 230553
80 lines
2.6 KiB
LLVM
80 lines
2.6 KiB
LLVM
; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx < %s | FileCheck %s
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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%struct.s2 = type { i64, <4 x float> }
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@ve = external global <4 x float>
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@n = external global i64
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; Function Attrs: nounwind
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define void @test1(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, i64 %d9, <4 x float> inreg %vs.coerce) #0 {
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entry:
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store <4 x float> %vs.coerce, <4 x float>* @ve, align 16
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ret void
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; CHECK-LABEL: @test1
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; CHECK: stvx 2,
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; CHECK: blr
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; CHECK-VSX-LABEL: @test1
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; CHECK-VSX: stxvw4x 34,
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; CHECK-VSX: blr
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}
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; Function Attrs: nounwind
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define void @test2(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, %struct.s2* byval nocapture readonly %vs) #0 {
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entry:
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%m = getelementptr inbounds %struct.s2* %vs, i64 0, i32 0
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%0 = load i64* %m, align 8
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store i64 %0, i64* @n, align 8
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%v = getelementptr inbounds %struct.s2* %vs, i64 0, i32 1
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%1 = load <4 x float>* %v, align 16
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store <4 x float> %1, <4 x float>* @ve, align 16
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ret void
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; CHECK-LABEL: @test2
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; CHECK-DAG: ld {{[0-9]+}}, 112(1)
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; CHECK-DAG: li [[REG16:[0-9]+]], 16
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; CHECK-DAG: addi [[REGB:[0-9]+]], 1, 112
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; CHECK-DAG: lvx 2, [[REGB]], [[REG16]]
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; CHECK: blr
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; CHECK-VSX-LABEL: @test2
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; CHECK-VSX-DAG: ld {{[0-9]+}}, 112(1)
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; CHECK-VSX-DAG: li [[REG16:[0-9]+]], 16
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; CHECK-VSX-DAG: addi [[REGB:[0-9]+]], 1, 112
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; CHECK-VSX-DAG: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]]
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; CHECK-VSX: blr
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}
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; Function Attrs: nounwind
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define void @test3(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, i64 %d9, %struct.s2* byval nocapture readonly %vs) #0 {
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entry:
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%m = getelementptr inbounds %struct.s2* %vs, i64 0, i32 0
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%0 = load i64* %m, align 8
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store i64 %0, i64* @n, align 8
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%v = getelementptr inbounds %struct.s2* %vs, i64 0, i32 1
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%1 = load <4 x float>* %v, align 16
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store <4 x float> %1, <4 x float>* @ve, align 16
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ret void
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; CHECK-LABEL: @test3
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; CHECK-DAG: ld {{[0-9]+}}, 128(1)
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; CHECK-DAG: li [[REG16:[0-9]+]], 16
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; CHECK-DAG: addi [[REGB:[0-9]+]], 1, 128
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; CHECK-DAG: lvx 2, [[REGB]], [[REG16]]
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; CHECK: blr
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; CHECK-VSX-LABEL: @test3
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; CHECK-VSX-DAG: ld {{[0-9]+}}, 128(1)
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; CHECK-VSX-DAG: li [[REG16:[0-9]+]], 16
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; CHECK-VSX-DAG: addi [[REGB:[0-9]+]], 1, 128
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; CHECK-VSX-DAG: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]]
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; CHECK-VSX: blr
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}
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attributes #0 = { nounwind }
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