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4a042ffefe
llvm-mirror/lib/Target/RISCV
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Alex Bradbury 4a042ffefe [RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions 
This restores support for selecting the SLLW/SRLW/SRAW instructions, which was
removed in rL348067 as the previous patterns made some unsafe assumptions.
Also see the related llvm-dev discussion
<http://lists.llvm.org/pipermail/llvm-dev/2018-December/128497.html>

Ultimately I didn't introduce a custom SelectionDAG node, but instead added a
DAG combine that inserts an AssertZext i5 on the shift amount for an i32
variable-length shift and also added an ANY_EXTEND DAG-combine which will
instead produce a SIGN_EXTEND for an i32 variable-length shift, increasing the
opportunity to safely select SLLW/SRLW/SRAW.

There are obviously different ways of addressing this (a number discussed in
the llvm-dev thread), so I'd welcome further feedback and comments.

Note that there are now some cases in
test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll where sraw/srlw/sllw is
selected even though sra/srl/sll could be used without any extra instructions.
Given both are semantically equivalent, there doesn't seem a good reason to
prefer one vs the other. Given that would require more logic to still select
sra/srl/sll in those cases, I've left it preferring the *w variants.

Differential Revision: https://reviews.llvm.org/D56264

llvm-svn: 350992
2019-01-12 07:32:31 +00:00
..
AsmParser [RISCV][MC] Add support for evaluating constant symbols as immediates 2019-01-10 15:33:17 +00:00
Disassembler [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00
InstPrinter [RISCV] Fix disassembling of fence instruction with invalid field 2018-10-11 22:49:13 +00:00
MCTargetDesc [RISCV] Properly evaluate fixup_riscv_pcrel_lo12 2018-12-20 14:52:15 +00:00
TargetInfo
Utils [RISCV][NFC] Define and use the new CA instruction format 2018-11-16 10:33:23 +00:00
CMakeLists.txt [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00
LLVMBuild.txt [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00
RISCV.h [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00
RISCV.td [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00
RISCVAsmPrinter.cpp Revert "[RISCV] implement li pseudo instruction" 2018-04-18 19:02:31 +00:00
RISCVCallingConv.td [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
RISCVExpandPseudoInsts.cpp [RISCV] Implement codegen for cmpxchg on RV32IA 2018-11-29 20:43:42 +00:00
RISCVFrameLowering.cpp [RISCV] Fix std::advance slowness 2018-08-24 23:13:59 +00:00
RISCVFrameLowering.h
RISCVInstrFormats.td [RISCV][NFC] Define and use the new CA instruction format 2018-11-16 10:33:23 +00:00
RISCVInstrFormatsC.td [RISCV][NFC] Define and use the new CA instruction format 2018-11-16 10:33:23 +00:00
RISCVInstrInfo.cpp [RISCV] Remove overzealous is64Bit checks 2018-10-04 14:30:03 +00:00
RISCVInstrInfo.h [RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot 2018-04-26 15:34:27 +00:00
RISCVInstrInfo.td [RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions 2019-01-12 07:32:31 +00:00
RISCVInstrInfoA.td [RISCV] Implement codegen for cmpxchg on RV32IA 2018-11-29 20:43:42 +00:00
RISCVInstrInfoC.td [RISCV] Add UNIMP instruction (32- and 16-bit forms) 2018-11-30 13:39:17 +00:00
RISCVInstrInfoD.td [RISCV] Add support for the various RISC-V FMA instruction variants 2018-12-13 10:49:05 +00:00
RISCVInstrInfoF.td [RISCV] Add support for the various RISC-V FMA instruction variants 2018-12-13 10:49:05 +00:00
RISCVInstrInfoM.td
RISCVISelDAGToDAG.cpp [RISCV] Introduce codegen patterns for instructions introduced in RV64I 2018-11-30 09:38:44 +00:00
RISCVISelLowering.cpp [RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions 2019-01-12 07:32:31 +00:00
RISCVISelLowering.h [TargetLowering][RISCV] Introduce isSExtCheaperThanZExt hook and implement for RISC-V 2018-11-30 09:56:54 +00:00
RISCVMachineFunctionInfo.h [RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv 2018-04-12 05:34:25 +00:00
RISCVMCInstLower.cpp
RISCVMergeBaseOffset.cpp Test commit. 2018-08-02 05:38:18 +00:00
RISCVRegisterInfo.cpp [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
RISCVRegisterInfo.h [RISCV] Set isReMaterializable on ADDI and LUI instructions 2018-05-17 15:51:37 +00:00
RISCVRegisterInfo.td [RISCV] Lower the tail pseudoinstruction 2018-05-23 22:44:08 +00:00
RISCVSubtarget.cpp
RISCVSubtarget.h [RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation 2018-05-15 01:28:50 +00:00
RISCVSystemOperands.td [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00
RISCVTargetMachine.cpp [Targets] Add errors for tiny and kernel codemodel on targets that don't support them 2018-12-07 12:10:23 +00:00
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h