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571a94ef5d
This has been a very painful missing feature that has made producing reduced testcases difficult. In particular the various registers determined for stack access during function lowering were necessary to avoid undefined register errors in a large percentage of cases. Implement a subset of the important fields that need to be preserved for AMDGPU. Most of the changes are to support targets parsing register fields and properly reporting errors. The biggest sort-of bug remaining is for fields that can be initialized from the IR section will be overwritten by a default initialized machineFunctionInfo section. Another remaining bug is the machineFunctionInfo section is still printed even if empty. llvm-svn: 356215
126 lines
4.4 KiB
C++
126 lines
4.4 KiB
C++
//===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// The AMDGPU TargetMachine interface definition for hw codgen targets.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
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#include "AMDGPUSubtarget.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/StringMap.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Target/TargetMachine.h"
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#include <memory>
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namespace llvm {
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//===----------------------------------------------------------------------===//
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// AMDGPU Target Machine (R600+)
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//===----------------------------------------------------------------------===//
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class AMDGPUTargetMachine : public LLVMTargetMachine {
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protected:
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std::unique_ptr<TargetLoweringObjectFile> TLOF;
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StringRef getGPUName(const Function &F) const;
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StringRef getFeatureString(const Function &F) const;
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public:
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static bool EnableLateStructurizeCFG;
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static bool EnableFunctionCalls;
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AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, TargetOptions Options,
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Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL);
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~AMDGPUTargetMachine() override;
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const TargetSubtargetInfo *getSubtargetImpl() const;
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const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override = 0;
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TargetLoweringObjectFile *getObjFileLowering() const override {
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return TLOF.get();
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}
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void adjustPassManager(PassManagerBuilder &) override;
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/// Get the integer value of a null pointer in the given address space.
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uint64_t getNullPointerValue(unsigned AddrSpace) const {
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return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
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AddrSpace == AMDGPUAS::REGION_ADDRESS) ? -1 : 0;
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}
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};
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//===----------------------------------------------------------------------===//
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// R600 Target Machine (R600 -> Cayman)
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//===----------------------------------------------------------------------===//
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class R600TargetMachine final : public AMDGPUTargetMachine {
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private:
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mutable StringMap<std::unique_ptr<R600Subtarget>> SubtargetMap;
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public:
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R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, TargetOptions Options,
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Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL, bool JIT);
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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const R600Subtarget *getSubtargetImpl(const Function &) const override;
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TargetTransformInfo getTargetTransformInfo(const Function &F) override;
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bool isMachineVerifierClean() const override {
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return false;
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}
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};
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//===----------------------------------------------------------------------===//
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// GCN Target Machine (SI+)
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//===----------------------------------------------------------------------===//
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class GCNTargetMachine final : public AMDGPUTargetMachine {
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private:
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mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap;
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public:
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GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, TargetOptions Options,
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Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL, bool JIT);
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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const GCNSubtarget *getSubtargetImpl(const Function &) const override;
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TargetTransformInfo getTargetTransformInfo(const Function &F) override;
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bool useIPRA() const override {
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return true;
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}
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yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
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yaml::MachineFunctionInfo *
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convertFuncInfoToYAML(const MachineFunction &MF) const override;
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bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
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PerFunctionMIParsingState &PFS,
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SMDiagnostic &Error,
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SMRange &SourceRange) const override;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
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