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llvm-mirror/test/MC/Mips/lld-expansion.s
Simon Atanasyan a4698bb735 [mips] Fix sc, scs, ll, lld instructions expanding
There are a couple of bugs with the sc, scs, ll, lld instructions expanding:

1. On R6 these instruction pack immediate offset into a 9-bit field. Now
if an immediate exceeds 9-bits assembler does not perform expansion and
just rejects such instruction.

2. On 64-bit non-PIC code if an operand is a symbol assembler generates
incorrect sequence of instructions. It uses R_MIPS_HI16 and R_MIPS_LO16
relocations and skips R_MIPS_HIGHEST and R_MIPS_HIGHER ones.

To solve these problems this patch:
- Introduces `mem_simm9_exp` to mark 9-bit memory immediate operands
which require expansion. Probably later all `mem_simm9` operands will be
able to migrate on `mem_simm9_exp` and we rename it to `mem_simm9`.

- Adds new `OPERAND_MEM_SIMM9` operand type and assigns it to the
`mem_simm9_exp`. That allows to know operand size in the `processInstruction`
method and decide whether we need to expand instruction.

- Adds `expandMem9Inst` method to expand instructions with 9-bit memory
immediate operand. This method just load immediate into a "base"
register used by origibal instruction:

   sc $2, 256($sp) => addiu  $1, $sp, 256
                      sc     $2, 0($1)

- Fix `expandMem16Inst` to support a correct set of relocations for
symbol loading in case of 64-bit non-PIC code.

   ll $12, symbol => lui    $12, 0
                         R_MIPS_HIGHEST symbol
                     daddiu $12, $12, 0
                         R_MIPS_HIGHER symbol
                     dsll   $12, $12, 16
                     daddiu $12, $12, 0
                         R_MIPS_HI16 symbol
                     dsll   $12, $12, 16
                     ll     $12, 0($12)
                         R_MIPS_LO16 symbol

- Fix `expandMem16Inst` to unify handling of 3 and 4 operands
instructions.

- Delete unused now `MipsTargetStreamer::emitSCWithSymOffset` method.

Task for next patches - implement expanding for other instructions use
`mem_simm9` operand and other `mem_simm##` operands.

Differential Revision: https://reviews.llvm.org/D70648
2019-11-27 00:43:25 +03:00

189 lines
8.0 KiB
ArmAsm

# RUN: llvm-mc -filetype=obj -triple mips64 -mcpu=mips64 %s -o - \
# RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefix=MIPS64
# RUN: llvm-mc -filetype=obj -triple mips64 -mcpu=mips64r6 %s -o - \
# RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefix=MIPS64R6
lld $2, 128($sp)
# MIPS64: d3 a2 00 80 lld $2, 128($sp)
# MIPS64R6: 7f a2 40 37 lld $2, 128($sp)
lld $2, -128($sp)
# MIPS64: d3 a2 ff 80 lld $2, -128($sp)
# MIPS64R6: 7f a2 c0 37 lld $2, -128($sp)
lld $2, 256($sp)
# MIPS64: d3 a2 01 00 lld $2, 256($sp)
# MIPS64R6: 67 a2 01 00 daddiu $2, $sp, 256
# MIPS64R6-NEXT: 7c 42 00 37 lld $2, 0($2)
lld $2, -257($sp)
# MIPS64: d3 a2 fe ff lld $2, -257($sp)
# MIPS64R6: 67 a2 fe ff daddiu $2, $sp, -257
# MIPS64R6-NEXT: 7c 42 00 37 lld $2, 0($2)
lld $2, 32767($sp)
# MIPS64: d3 a2 7f ff lld $2, 32767($sp)
# MIPS64R6: 67 a2 7f ff daddiu $2, $sp, 32767
# MIPS64R6-NEXT: 7c 42 00 37 lld $2, 0($2)
lld $2, 32768($sp)
# MIPS64: 3c 02 00 01 lui $2, 1
# MIPS64-NEXT: 00 5d 10 2d daddu $2, $2, $sp
# MIPS64-NEXT: d0 42 80 00 lld $2, -32768($2)
# MIPS64R6: 34 02 80 00 ori $2, $zero, 32768
# MIPS64R6-NEXT: 00 5d 10 2d daddu $2, $2, $sp
# MIPS64R6-NEXT: 7c 42 00 37 lld $2, 0($2)
lld $2, -32768($sp)
# MIPS64: d3 a2 80 00 lld $2, -32768($sp)
# MIPS64R6: 67 a2 80 00 daddiu $2, $sp, -32768
# MIPS64R6-NEXT: 7c 42 00 37 lld $2, 0($2)
lld $2, -32769($sp)
# MIPS64: 3c 02 ff ff lui $2, 65535
# MIPS64-NEXT: 00 5d 10 2d daddu $2, $2, $sp
# MIPS64-NEXT: d0 42 7f ff lld $2, 32767($2)
# MIPS64R6: 3c 02 ff ff aui $2, $zero, 65535
# MIPS64R6-NEXT: 34 42 7f ff ori $2, $2, 32767
# MIPS64R6-NEXT: 00 5d 10 2d daddu $2, $2, $sp
# MIPS64R6-NEXT: 7c 42 00 37 lld $2, 0($2)
lld $2, 2147483648($sp)
# MIPS64: 34 02 80 00 ori $2, $zero, 32768
# MIPS64-NEXT: 00 02 14 38 dsll $2, $2, 16
# MIPS64-NEXT: 00 5d 10 2d daddu $2, $2, $sp
# MIPS64-NEXT: d0 42 00 00 lld $2, 0($2)
# MIPS64R6: 34 02 80 00 ori $2, $zero, 32768
# MIPS64R6-NEXT: 00 02 14 38 dsll $2, $2, 16
# MIPS64R6-NEXT: 00 5d 10 2d daddu $2, $2, $sp
# MIPS64R6-NEXT: 7c 42 00 37 lld $2, 0($2)
lld $2, -2147483648($sp)
# MIPS64: 3c 02 80 00 lui $2, 32768
# MIPS64-NEXT: 00 5d 10 2d daddu $2, $2, $sp
# MIPS64-NEXT: d0 42 00 00 lld $2, 0($2)
# MIPS64R6: 3c 02 80 00 aui $2, $zero, 32768
# MIPS64R6-NEXT: 00 5d 10 2d daddu $2, $2, $sp
# MIPS64R6-NEXT: 7c 42 00 37 lld $2, 0($2)
lld $2, 9223372036853775808($sp)
# MIPS64: 3c 02 7f ff lui $2, 32767
# MIPS64-NEXT: 34 42 ff ff ori $2, $2, 65535
# MIPS64-NEXT: 00 02 14 38 dsll $2, $2, 16
# MIPS64-NEXT: 34 42 ff f1 ori $2, $2, 65521
# MIPS64-NEXT: 00 02 14 38 dsll $2, $2, 16
# MIPS64-NEXT: 00 5d 10 2d daddu $2, $2, $sp
# MIPS64-NEXT: d0 42 bd c0 lld $2, -16960($2)
# MIPS64R6: 3c 02 7f ff aui $2, $zero, 32767
# MIPS64R6-NEXT: 34 42 ff ff ori $2, $2, 65535
# MIPS64R6-NEXT: 00 02 14 38 dsll $2, $2, 16
# MIPS64R6-NEXT: 34 42 ff f0 ori $2, $2, 65520
# MIPS64R6-NEXT: 00 02 14 38 dsll $2, $2, 16
# MIPS64R6-NEXT: 34 42 bd c0 ori $2, $2, 48576
# MIPS64R6-NEXT: 00 5d 10 2d daddu $2, $2, $sp
# MIPS64R6-NEXT: 7c 42 00 37 lld $2, 0($2)
lld $12, symbol
# MIPS64: 3c 0c 00 00 lui $12, 0
# MIPS64-NEXT: R_MIPS_HIGHEST/R_MIPS_NONE/R_MIPS_NONE symbol
# MIPS64-NEXT: 65 8c 00 00 daddiu $12, $12, 0
# MIPS64-NEXT: R_MIPS_HIGHER/R_MIPS_NONE/R_MIPS_NONE symbol
# MIPS64-NEXT: 00 0c 64 38 dsll $12, $12, 16
# MIPS64-NEXT: 65 8c 00 00 daddiu $12, $12, 0
# MIPS64-NEXT: R_MIPS_HI16/R_MIPS_NONE/R_MIPS_NONE symbol
# MIPS64-NEXT: 00 0c 64 38 dsll $12, $12, 16
# MIPS64-NEXT: d1 8c 00 00 lld $12, 0($12)
# MIPS64-NEXT: R_MIPS_LO16/R_MIPS_NONE/R_MIPS_NONE symbol
# MIPS64R6: 3c 0c 00 00 aui $12, $zero, 0
# MIPS64R6-NEXT: R_MIPS_HIGHEST/R_MIPS_NONE/R_MIPS_NONE symbol
# MIPS64R6-NEXT: 3c 01 00 00 aui $1, $zero, 0
# MIPS64R6-NEXT: R_MIPS_HI16/R_MIPS_NONE/R_MIPS_NONE symbol
# MIPS64R6-NEXT: 65 8c 00 00 daddiu $12, $12, 0
# MIPS64R6-NEXT: R_MIPS_HIGHER/R_MIPS_NONE/R_MIPS_NONE symbol
# MIPS64R6-NEXT: 64 21 00 00 daddiu $1, $1, 0
# MIPS64R6-NEXT: R_MIPS_LO16/R_MIPS_NONE/R_MIPS_NONE symbol
# MIPS64R6-NEXT: 00 0c 60 3c dsll32 $12, $12, 0
# MIPS64R6-NEXT: 01 81 60 2d daddu $12, $12, $1
# MIPS64R6-NEXT: 7d 8c 00 37 lld $12, 0($12)
lld $12, symbol($3)
# MIPS64: 3c 0c 00 00 lui $12, 0
# MIPS64-NEXT: R_MIPS_HIGHEST/R_MIPS_NONE/R_MIPS_NONE symbol
# MIPS64-NEXT: 65 8c 00 00 daddiu $12, $12, 0
# MIPS64-NEXT: R_MIPS_HIGHER/R_MIPS_NONE/R_MIPS_NONE symbol
# MIPS64-NEXT: 00 0c 64 38 dsll $12, $12, 16
# MIPS64-NEXT: 65 8c 00 00 daddiu $12, $12, 0
# MIPS64-NEXT: R_MIPS_HI16/R_MIPS_NONE/R_MIPS_NONE symbol
# MIPS64-NEXT: 00 0c 64 38 dsll $12, $12, 16
# MIPS64-NEXT: 01 83 60 2d daddu $12, $12, $3
# MIPS64-NEXT: d1 8c 00 00 lld $12, 0($12)
# MIPS64-NEXT: R_MIPS_LO16/R_MIPS_NONE/R_MIPS_NONE symbol
# MIPS64R6-NEXT: 3c 0c 00 00 aui $12, $zero, 0
# MIPS64R6-NEXT: R_MIPS_HIGHEST/R_MIPS_NONE/R_MIPS_NONE symbol
# MIPS64R6-NEXT: 3c 01 00 00 aui $1, $zero, 0
# MIPS64R6-NEXT: R_MIPS_HI16/R_MIPS_NONE/R_MIPS_NONE symbol
# MIPS64R6-NEXT: 65 8c 00 00 daddiu $12, $12, 0
# MIPS64R6-NEXT: R_MIPS_HIGHER/R_MIPS_NONE/R_MIPS_NONE symbol
# MIPS64R6-NEXT: 64 21 00 00 daddiu $1, $1, 0
# MIPS64R6-NEXT: R_MIPS_LO16/R_MIPS_NONE/R_MIPS_NONE symbol
# MIPS64R6-NEXT: 00 0c 60 3c dsll32 $12, $12, 0
# MIPS64R6-NEXT: 01 81 60 2d daddu $12, $12, $1
# MIPS64R6-NEXT: 01 83 60 2d daddu $12, $12, $3
# MIPS64R6-NEXT: 7d 8c 00 37 lld $12, 0($12)
lld $12, symbol+8
# MIPS64: 3c 0c 00 00 lui $12, 0
# MIPS64-NEXT: R_MIPS_HIGHEST/R_MIPS_NONE/R_MIPS_NONE symbol+0x8
# MIPS64-NEXT: 65 8c 00 00 daddiu $12, $12, 0
# MIPS64-NEXT: R_MIPS_HIGHER/R_MIPS_NONE/R_MIPS_NONE symbol+0x8
# MIPS64-NEXT: 00 0c 64 38 dsll $12, $12, 16
# MIPS64-NEXT: 65 8c 00 00 daddiu $12, $12, 0
# MIPS64-NEXT: R_MIPS_HI16/R_MIPS_NONE/R_MIPS_NONE symbol+0x8
# MIPS64-NEXT: 00 0c 64 38 dsll $12, $12, 16
# MIPS64-NEXT: d1 8c 00 00 lld $12, 0($12)
# MIPS64-NEXT: R_MIPS_LO16/R_MIPS_NONE/R_MIPS_NONE symbol+0x8
# MIPS64R6-NEXT: 3c 0c 00 00 aui $12, $zero, 0
# MIPS64R6-NEXT: R_MIPS_HIGHEST/R_MIPS_NONE/R_MIPS_NONE symbol+0x8
# MIPS64R6-NEXT: 3c 01 00 00 aui $1, $zero, 0
# MIPS64R6-NEXT: R_MIPS_HI16/R_MIPS_NONE/R_MIPS_NONE symbol+0x8
# MIPS64R6-NEXT: 65 8c 00 00 daddiu $12, $12, 0
# MIPS64R6-NEXT: R_MIPS_HIGHER/R_MIPS_NONE/R_MIPS_NONE symbol+0x8
# MIPS64R6-NEXT: 64 21 00 00 daddiu $1, $1, 0
# MIPS64R6-NEXT: R_MIPS_LO16/R_MIPS_NONE/R_MIPS_NONE symbol+0x8
# MIPS64R6-NEXT: 00 0c 60 3c dsll32 $12, $12, 0
# MIPS64R6-NEXT: 01 81 60 2d daddu $12, $12, $1
# MIPS64R6-NEXT: 7d 8c 00 37 lld $12, 0($12)
.option pic2
lld $12, symbol
# MIPS64: df 8c 00 00 ld $12, 0($gp)
# MIPS64-NEXT: R_MIPS_GOT_DISP/R_MIPS_NONE/R_MIPS_NONE symbol
# MIPS64-NEXT: d1 8c 00 00 lld $12, 0($12)
# MIPS64R6: df 8c 00 00 ld $12, 0($gp)
# MIPS64R6-NEXT: R_MIPS_GOT_DISP/R_MIPS_NONE/R_MIPS_NONE symbol
# MIPS64R6-NEXT: 7d 8c 00 37 lld $12, 0($12)
lld $12, symbol+8
# MIPS64: df 8c 00 00 ld $12, 0($gp)
# MIPS64-NEXT: R_MIPS_GOT_DISP/R_MIPS_NONE/R_MIPS_NONE symbol
# MIPS64-NEXT: d1 8c 00 08 lld $12, 8($12)
# MIPS64R6: df 8c 00 00 ld $12, 0($gp)
# MIPS64R6-NEXT: R_MIPS_GOT_DISP/R_MIPS_NONE/R_MIPS_NONE symbol
# MIPS64R6-NEXT: 65 8c 00 08 daddiu $12, $12, 8
# MIPS64R6-NEXT: 7d 8c 00 37 lld $12, 0($12)