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llvm-mirror/test/CodeGen/X86/inline-asm.ll
Eric Christopher ca7ae418a5 Check register class matching instead of width of type matching
when determining validity of matching constraint. Allow i1
types access to the GR8 reg class for x86.

Fixes PR10352 and rdar://9777108

llvm-svn: 135180
2011-07-14 20:13:52 +00:00

46 lines
1.2 KiB
LLVM

; RUN: llc < %s -march=x86
define i32 @test1() nounwind {
; Dest is AX, dest type = i32.
%tmp4 = call i32 asm sideeffect "FROB $0", "={ax}"()
ret i32 %tmp4
}
define void @test2(i32 %V) nounwind {
; input is AX, in type = i32.
call void asm sideeffect "FROB $0", "{ax}"(i32 %V)
ret void
}
define void @test3() nounwind {
; FP constant as a memory operand.
tail call void asm sideeffect "frob $0", "m"( float 0x41E0000000000000)
ret void
}
define void @test4() nounwind {
; J means a constant in range 0 to 63.
tail call void asm sideeffect "bork $0", "J"(i32 37) nounwind
ret void
}
; rdar://9738585
define i32 @test5() nounwind {
entry:
%0 = tail call i32 asm "test", "=l,~{dirflag},~{fpsr},~{flags}"() nounwind
ret i32 0
}
; rdar://9777108 PR10352
define void @test6(i1 zeroext %desired) nounwind {
entry:
tail call void asm sideeffect "foo $0", "q,~{dirflag},~{fpsr},~{flags}"(i1 %desired) nounwind
ret void
}
define void @test7(i1 zeroext %desired, i32* %p) nounwind {
entry:
%0 = tail call i8 asm sideeffect "xchg $0, $1", "=r,*m,0,~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %p, i1 %desired) nounwind
ret void
}