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llvm-mirror/test/CodeGen/X86/peep-vector-extract-insert.ll
Jakob Stoklund Olesen 5d6a4584d9 Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.
Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.

This also makes the AVX variants redundant.

llvm-svn: 145440
2011-11-29 22:27:25 +00:00

13 lines
436 B
LLVM

; RUN: llc < %s -march=x86-64 | grep {xorps %xmm0, %xmm0} | count 2
define float @foo(<4 x float> %a) {
%b = insertelement <4 x float> %a, float 0.0, i32 3
%c = extractelement <4 x float> %b, i32 3
ret float %c
}
define float @bar(float %a) {
%b = insertelement <4 x float> <float 0x400B333340000000, float 4.5, float 0.0, float 0x4022666660000000>, float %a, i32 3
%c = extractelement <4 x float> %b, i32 2
ret float %c
}