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d09b64fc25
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
42 lines
974 B
LLVM
42 lines
974 B
LLVM
; RUN: llc < %s -mcpu=generic -march=x86 | FileCheck %s
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;; Simple case
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define i32 @test1(i8 %x) nounwind readnone {
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%A = and i8 %x, -32
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%B = zext i8 %A to i32
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ret i32 %B
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}
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; CHECK: test1
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; CHECK: movzbl
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; CHECK-NEXT: andl {{.*}}224
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;; Multiple uses of %x but easily extensible.
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define i32 @test2(i8 %x) nounwind readnone {
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%A = and i8 %x, -32
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%B = zext i8 %A to i32
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%C = or i8 %x, 63
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%D = zext i8 %C to i32
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%E = add i32 %B, %D
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ret i32 %E
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}
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; CHECK: test2
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; CHECK: movzbl
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; CHECK: orl $63
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; CHECK: andl $224
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declare void @use(i32, i8)
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;; Multiple uses of %x where we shouldn't extend the load.
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define void @test3(i8 %x) nounwind readnone {
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%A = and i8 %x, -32
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%B = zext i8 %A to i32
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call void @use(i32 %B, i8 %x)
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ret void
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}
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; CHECK: test3
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; CHECK: movzbl {{[0-9]+}}(%esp), [[REGISTER:%e[a-z]{2}]]
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; CHECK-NEXT: movl [[REGISTER]], 4(%esp)
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; CHECK-NEXT: andl $224, [[REGISTER]]
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; CHECK-NEXT: movl [[REGISTER]], (%esp)
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; CHECK-NEXT: call{{.*}}use
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