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118 lines
5.7 KiB
YAML
118 lines
5.7 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck -check-prefix GCN %s
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#
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---
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name: _amdgpu_ps_main
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alignment: 1
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sgpr_128 }
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- { id: 1, class: sreg_32_xm0, preferred-register: '%2' }
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- { id: 2, class: sreg_32_xm0, preferred-register: '%1' }
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machineFunctionInfo:
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argumentInfo:
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privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
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privateSegmentWaveByteOffset: { reg: '$sgpr33' }
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body: |
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; GCN-LABEL: name: _amdgpu_ps_main
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: [[V_TRUNC_F32_e32_:%[0-9]+]]:vgpr_32 = V_TRUNC_F32_e32 undef %4:vgpr_32, implicit $exec
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; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_TRUNC_F32_e32_]], implicit $exec
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; GCN: [[V_LSHRREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e32 4, [[V_CVT_U32_F32_e32_]], implicit $exec
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; GCN: undef %11.sub0:vreg_128 = V_MUL_LO_I32 [[V_LSHRREV_B32_e32_]], 3, implicit $exec
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; GCN: %11.sub3:vreg_128 = COPY %11.sub0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
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; GCN: bb.1:
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; GCN: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
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; GCN: [[COPY:%[0-9]+]]:vreg_128 = COPY %11
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; GCN: %11.sub3:vreg_128 = V_ADD_U32_e32 target-flags(amdgpu-rel32-lo) 1, [[COPY]].sub3, implicit $exec
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; GCN: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xm0 = S_ADD_I32 [[S_ADD_I32_]], 1, implicit-def dead $scc
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; GCN: S_CMP_LT_U32 [[S_ADD_I32_]], 3, implicit-def $scc
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit killed $scc
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; GCN: S_BRANCH %bb.2
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; GCN: bb.2:
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; GCN: successors: %bb.5(0x40000000), %bb.3(0x40000000)
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; GCN: S_CBRANCH_SCC1 %bb.5, implicit undef $scc
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; GCN: S_BRANCH %bb.3
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; GCN: bb.3:
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; GCN: successors: %bb.4(0x80000000)
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; GCN: dead %16:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN [[COPY]].sub3, undef %17:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4)
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; GCN: dead %18:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
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; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 $exec, -1, implicit-def dead $scc
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; GCN: dead %20:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; GCN: bb.4:
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; GCN: successors: %bb.4(0x7c000000), %bb.6(0x04000000)
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; GCN: $vcc = COPY [[S_AND_B64_]]
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; GCN: S_CBRANCH_VCCNZ %bb.4, implicit killed $vcc
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; GCN: S_BRANCH %bb.6
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; GCN: bb.5:
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; GCN: [[V_MUL_F32_e32_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e32 target-flags(amdgpu-gotprel) 0, %11.sub0, implicit $exec
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; GCN: [[V_MIN_F32_e32_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e32 1106771968, [[V_MUL_F32_e32_]], implicit $exec
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; GCN: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = nnan arcp contract reassoc V_MAD_F32 0, [[V_MIN_F32_e32_]], 0, 0, 0, 0, 0, 0, implicit $exec
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; GCN: [[V_MAD_F32_1:%[0-9]+]]:vgpr_32 = nnan arcp contract reassoc V_MAD_F32 0, [[V_MAD_F32_]], 0, 0, 0, 0, 0, 0, implicit $exec
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; GCN: [[V_MAD_F32_2:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[V_MAD_F32_1]], 0, 0, 0, 0, 0, 0, implicit $exec
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; GCN: [[V_CVT_PKRTZ_F16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, [[V_MAD_F32_2]], 0, undef %27:vgpr_32, 0, 0, implicit $exec
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; GCN: EXP_DONE 0, [[V_CVT_PKRTZ_F16_F32_e64_]], undef %28:vgpr_32, undef %29:vgpr_32, undef %30:vgpr_32, -1, -1, 15, implicit $exec
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; GCN: S_ENDPGM 0
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; GCN: bb.6:
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; GCN: S_ENDPGM 0
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bb.0:
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%10:vgpr_32 = V_TRUNC_F32_e32 undef %11:vgpr_32, implicit $exec
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%12:vgpr_32 = V_CVT_U32_F32_e32 killed %10, implicit $exec
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%50:vgpr_32 = V_LSHRREV_B32_e32 4, killed %12, implicit $exec
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%51:vgpr_32 = V_MUL_LO_I32 killed %50, 3, implicit $exec
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undef %52.sub0:vreg_128 = COPY %51
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%52.sub3:vreg_128 = COPY %51
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%9:sreg_32_xm0 = S_MOV_B32 0
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%70:sreg_32_xm0 = COPY killed %9
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%71:vreg_128 = COPY killed %52
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bb.1:
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successors: %bb.1(0x7c000000), %bb.2(0x04000000)
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%53:vreg_128 = COPY killed %71
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%1:sreg_32_xm0 = COPY killed %70
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%57:vgpr_32 = V_ADD_U32_e32 target-flags(amdgpu-rel32-lo) 1, %53.sub3, implicit $exec
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%55:vreg_128 = COPY %53
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%55.sub3:vreg_128 = COPY killed %57
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%2:sreg_32_xm0 = S_ADD_I32 killed %1, 1, implicit-def dead $scc
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S_CMP_LT_U32 %2, 3, implicit-def $scc
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%54:vreg_128 = COPY %55
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%70:sreg_32_xm0 = COPY killed %2
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%71:vreg_128 = COPY killed %54
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S_CBRANCH_SCC1 %bb.1, implicit killed $scc
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S_BRANCH %bb.2
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bb.2:
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S_CBRANCH_SCC1 %bb.5, implicit undef $scc
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S_BRANCH %bb.3
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bb.3:
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dead %22:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %53.sub3, undef %24:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4)
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dead %60:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
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%36:sreg_64 = S_AND_B64 $exec, -1, implicit-def dead $scc
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dead %67:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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bb.4:
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successors: %bb.4(0x7c000000), %bb.6(0x04000000)
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$vcc = COPY %36
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S_CBRANCH_VCCNZ %bb.4, implicit killed $vcc
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S_BRANCH %bb.6
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bb.5:
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%39:vgpr_32 = V_MUL_F32_e32 target-flags(amdgpu-gotprel) 0, killed %55.sub0, implicit $exec
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%41:vgpr_32 = V_MIN_F32_e32 1106771968, killed %39, implicit $exec
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%42:vgpr_32 = nnan arcp contract reassoc V_MAD_F32 0, killed %41, 0, 0, 0, 0, 0, 0, implicit $exec
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%43:vgpr_32 = nnan arcp contract reassoc V_MAD_F32 0, killed %42, 0, 0, 0, 0, 0, 0, implicit $exec
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%44:vgpr_32 = V_MAD_F32 0, killed %43, 0, 0, 0, 0, 0, 0, implicit $exec
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%45:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, killed %44, 0, undef %46:vgpr_32, 0, 0, implicit $exec
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EXP_DONE 0, killed %45, undef %47:vgpr_32, undef %48:vgpr_32, undef %49:vgpr_32, -1, -1, 15, implicit $exec
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S_ENDPGM 0
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bb.6:
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S_ENDPGM 0
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...
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