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llvm-mirror/test/CodeGen/AMDGPU/insert-skips-kill-uncond.mir
cdevadas 4033a61f5d Resubmit: [AMDGPU] Invert the handling of skip insertion.
The current implementation of skip insertion (SIInsertSkip) makes it a
mandatory pass required for correctness. Initially, the idea was to
have an optional pass. This patch inserts the s_cbranch_execz upfront
during SILowerControlFlow to skip over the sections of code when no
lanes are active. Later, SIRemoveShortExecBranches removes the skips
for short branches, unless there is a sideeffect and the skip branch is
really necessary.

This new pass will replace the handling of skip insertion in the
existing SIInsertSkip Pass.

Differential revision: https://reviews.llvm.org/D68092
2020-01-22 13:18:32 +09:00

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# RUN: llc -march=amdgcn -mcpu=polaris10 -run-pass si-insert-skips -amdgpu-skip-threshold-legacy=1 %s -o - | FileCheck %s
# https://bugs.freedesktop.org/show_bug.cgi?id=99019
--- |
define amdgpu_ps void @kill_uncond_branch() {
ret void
}
...
---
# CHECK-LABEL: name: kill_uncond_branch
# CHECK: bb.0:
# CHECK: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
# CHECK: bb.1:
# CHECK: V_CMPX_LE_F32_e32
# CHECK-NEXT: S_CBRANCH_EXECNZ %bb.2, implicit $exec
# CHECK: bb.3:
# CHECK-NEXT: EXP_DONE
# CHECK: S_ENDPGM 0
# CHECK: bb.2:
# CHECK: S_ENDPGM 0
name: kill_uncond_branch
body: |
bb.0:
successors: %bb.1
S_CBRANCH_VCCNZ %bb.1, implicit $vcc
bb.1:
successors: %bb.2
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
SI_KILL_F32_COND_IMM_TERMINATOR $vgpr0, 0, 3, implicit-def $exec, implicit-def $vcc, implicit-def $scc, implicit $exec
S_BRANCH %bb.2
bb.2:
S_ENDPGM 0