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https://github.com/RPCS3/llvm-mirror.git
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222 lines
8.4 KiB
LLVM
222 lines
8.4 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; GCN-LABEL: {{^}}lsh8_or_and:
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; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x6050400
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; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
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define amdgpu_kernel void @lsh8_or_and(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
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%tmp = load i32, i32 addrspace(1)* %gep, align 4
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%tmp2 = shl i32 %tmp, 8
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%tmp3 = and i32 %arg1, 255
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%tmp4 = or i32 %tmp2, %tmp3
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store i32 %tmp4, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}lsr24_or_and:
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; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x7060503
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; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
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define amdgpu_kernel void @lsr24_or_and(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
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%tmp = load i32, i32 addrspace(1)* %gep, align 4
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%tmp2 = lshr i32 %tmp, 24
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%tmp3 = and i32 %arg1, 4294967040 ; 0xffffff00
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%tmp4 = or i32 %tmp2, %tmp3
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store i32 %tmp4, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}and_or_lsr24:
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; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x7060503
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; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
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define amdgpu_kernel void @and_or_lsr24(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
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%tmp = load i32, i32 addrspace(1)* %gep, align 4
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%tmp2 = and i32 %tmp, 4294967040 ; 0xffffff00
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%tmp3 = lshr i32 %arg1, 24
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%tmp4 = or i32 %tmp2, %tmp3
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%tmp5 = xor i32 %tmp4, -2147483648
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store i32 %tmp5, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}and_or_and:
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; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x7020500
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; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
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define amdgpu_kernel void @and_or_and(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
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%tmp = load i32, i32 addrspace(1)* %gep, align 4
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%tmp2 = and i32 %tmp, -16711936
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%tmp3 = and i32 %arg1, 16711935
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%tmp4 = or i32 %tmp2, %tmp3
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store i32 %tmp4, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}lsh8_or_lsr24:
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; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x6050403
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; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
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define amdgpu_kernel void @lsh8_or_lsr24(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
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%tmp = load i32, i32 addrspace(1)* %gep, align 4
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%tmp2 = shl i32 %tmp, 8
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%tmp3 = lshr i32 %arg1, 24
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%tmp4 = or i32 %tmp2, %tmp3
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store i32 %tmp4, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}lsh16_or_lsr24:
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; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x5040c03
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; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
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define amdgpu_kernel void @lsh16_or_lsr24(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
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%tmp = load i32, i32 addrspace(1)* %gep, align 4
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%tmp2 = shl i32 %tmp, 16
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%tmp3 = lshr i32 %arg1, 24
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%tmp4 = or i32 %tmp2, %tmp3
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store i32 %tmp4, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}and_xor_and:
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; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x7020104
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; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
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define amdgpu_kernel void @and_xor_and(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
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%tmp = load i32, i32 addrspace(1)* %gep, align 4
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%tmp2 = and i32 %tmp, -16776961
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%tmp3 = and i32 %arg1, 16776960
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%tmp4 = xor i32 %tmp2, %tmp3
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store i32 %tmp4, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}and_or_or_and:
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; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0xffff0500
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; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
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define amdgpu_kernel void @and_or_or_and(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
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%tmp = load i32, i32 addrspace(1)* %gep, align 4
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%and = and i32 %tmp, 16711935 ; 0x00ff00ff
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%tmp1 = and i32 %arg1, 4294967040 ; 0xffffff00
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%tmp2 = or i32 %tmp1, -65536
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%tmp3 = or i32 %tmp2, %and
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store i32 %tmp3, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}and_or_and_shl:
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; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x50c0c00
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; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
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define amdgpu_kernel void @and_or_and_shl(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
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%tmp = load i32, i32 addrspace(1)* %gep, align 4
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%tmp2 = shl i32 %tmp, 16
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%tmp3 = and i32 %arg1, 65535
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%tmp4 = or i32 %tmp2, %tmp3
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%and = and i32 %tmp4, 4278190335
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store i32 %and, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}or_and_or:
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; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x7020104
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; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
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define amdgpu_kernel void @or_and_or(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
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%tmp = load i32, i32 addrspace(1)* %gep, align 4
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%or1 = or i32 %tmp, 16776960 ; 0x00ffff00
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%or2 = or i32 %arg1, 4278190335 ; 0xff0000ff
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%and = and i32 %or1, %or2
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store i32 %and, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}known_ffff0500:
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; GCN-DAG: v_mov_b32_e32 [[MASK:v[0-9]+]], 0xffff0500
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; GCN-DAG: v_mov_b32_e32 [[RES:v[0-9]+]], 0xffff8004
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; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
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; GCN: store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
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define amdgpu_kernel void @known_ffff0500(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
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%load = load i32, i32 addrspace(1)* %gep, align 4
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%mask1 = or i32 %arg1, 32768 ; 0x8000
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%mask2 = or i32 %load, 4
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%and = and i32 %mask2, 16711935 ; 0x00ff00ff
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%tmp1 = and i32 %mask1, 4294967040 ; 0xffffff00
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%tmp2 = or i32 %tmp1, 4294901760 ; 0xffff0000
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%tmp3 = or i32 %tmp2, %and
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store i32 %tmp3, i32 addrspace(1)* %gep, align 4
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%v = and i32 %tmp3, 4294934532 ; 0xffff8004
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store i32 %v, i32 addrspace(1)* %arg, align 4
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ret void
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}
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; GCN-LABEL: {{^}}known_050c0c00:
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; GCN-DAG: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x50c0c00
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; GCN-DAG: v_mov_b32_e32 [[RES:v[0-9]+]], 4{{$}}
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; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
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; GCN: store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
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define amdgpu_kernel void @known_050c0c00(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
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%tmp = load i32, i32 addrspace(1)* %gep, align 4
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%tmp2 = shl i32 %tmp, 16
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%mask = or i32 %arg1, 4
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%tmp3 = and i32 %mask, 65535
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%tmp4 = or i32 %tmp2, %tmp3
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%and = and i32 %tmp4, 4278190335
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store i32 %and, i32 addrspace(1)* %gep, align 4
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%v = and i32 %and, 16776964
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store i32 %v, i32 addrspace(1)* %arg, align 4
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ret void
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}
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; GCN-LABEL: {{^}}known_ffff8004:
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; GCN-DAG: v_mov_b32_e32 [[MASK:v[0-9]+]], 0xffff0500
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; GCN-DAG: v_mov_b32_e32 [[RES:v[0-9]+]], 0xffff8004
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; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
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; GCN: store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
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define amdgpu_kernel void @known_ffff8004(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
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%load = load i32, i32 addrspace(1)* %gep, align 4
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%mask1 = or i32 %arg1, 4
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%mask2 = or i32 %load, 32768 ; 0x8000
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%and = and i32 %mask1, 16711935 ; 0x00ff00ff
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%tmp1 = and i32 %mask2, 4294967040 ; 0xffffff00
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%tmp2 = or i32 %tmp1, 4294901760 ; 0xffff0000
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%tmp3 = or i32 %tmp2, %and
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store i32 %tmp3, i32 addrspace(1)* %gep, align 4
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%v = and i32 %tmp3, 4294934532 ; 0xffff8004
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store i32 %v, i32 addrspace(1)* %arg, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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