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b9148f5d85
Summary: Extend cachepolicy operand in the new VMEM buffer intrinsics to supply information whether the buffer data is swizzled. Also, propagate this information to MIR. Intrinsics updated: int_amdgcn_raw_buffer_load int_amdgcn_raw_buffer_load_format int_amdgcn_raw_buffer_store int_amdgcn_raw_buffer_store_format int_amdgcn_raw_tbuffer_load int_amdgcn_raw_tbuffer_store int_amdgcn_struct_buffer_load int_amdgcn_struct_buffer_load_format int_amdgcn_struct_buffer_store int_amdgcn_struct_buffer_store_format int_amdgcn_struct_tbuffer_load int_amdgcn_struct_tbuffer_store Furthermore, disable merging of VMEM buffer instructions in SI Load/Store optimizer, if the "swizzled" bit on the instruction is on. The default value of the bit is 0, meaning that data in buffer is linear and buffer instructions can be merged. There is no difference in the generated code with this commit. However, in the future it will be expected that front-ends use buffer intrinsics with correct "swizzled" bit set. Reviewers: arsenm, nhaehnle, tpr Reviewed By: nhaehnle Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68200 llvm-svn: 373491
225 lines
6.2 KiB
YAML
225 lines
6.2 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: vmem_write_sgpr
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# GCN: BUFFER_LOAD_DWORD_OFFEN
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# GCN-NEXT: V_NOP
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# GCN-NEXT: S_MOV_B32
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---
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name: vmem_write_sgpr
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body: |
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bb.0:
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$sgpr4 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec
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$sgpr0 = S_MOV_B32 0
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...
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# GCN-LABEL: name: vmem_smem_write_sgpr
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# GCN: BUFFER_LOAD_DWORD_OFFEN
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# GCN-NEXT: V_NOP
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# GCN-NEXT: S_LOAD_DWORD_IMM
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---
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name: vmem_smem_write_sgpr
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body: |
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bb.0:
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$sgpr4 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec
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$sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
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...
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# GCN-LABEL: name: vmem_snop_write_sgpr
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# GCN: BUFFER_LOAD_DWORD_OFFEN
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# GCN-NEXT: S_NOP
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# GCN-NEXT: V_NOP
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# GCN-NEXT: S_MOV_B32
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---
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name: vmem_snop_write_sgpr
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body: |
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bb.0:
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$sgpr4 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec
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S_NOP 0
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$sgpr0 = S_MOV_B32 0
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...
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# GCN-LABEL: name: vmem_valu_write_sgpr
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# GCN: BUFFER_LOAD_DWORD_OFFEN
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# GCN-NEXT: V_ADD_F32
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# GCN-NEXT: S_MOV_B32
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---
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name: vmem_valu_write_sgpr
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body: |
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bb.0:
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$sgpr4 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec
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$vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $exec
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$sgpr0 = S_MOV_B32 0
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...
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# GCN-LABEL: name: vmem_swait0_write_sgpr
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# GCN: BUFFER_LOAD_DWORD_OFFEN
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# GCN-NEXT: S_WAITCNT
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# GCN-NEXT: S_MOV_B32
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---
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name: vmem_swait0_write_sgpr
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body: |
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bb.0:
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$sgpr4 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec
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S_WAITCNT 0
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$sgpr0 = S_MOV_B32 0
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...
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# GCN-LABEL: name: vmem_swait_any_write_sgpr
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# GCN: BUFFER_LOAD_DWORD_OFFEN
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# GCN-NEXT: S_WAITCNT
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# GCN-NEXT: V_NOP
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# GCN-NEXT: S_MOV_B32
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---
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name: vmem_swait_any_write_sgpr
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body: |
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bb.0:
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$sgpr4 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec
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S_WAITCNT 1
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$sgpr0 = S_MOV_B32 0
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...
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# GCN-LABEL: name: vmem_write_exec_impread
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# GCN: BUFFER_LOAD_DWORD_OFFEN
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# GCN: V_NOP
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# GCN-NEXT: S_MOV_B64
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---
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name: vmem_write_exec_impread
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body: |
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bb.0:
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$sgpr4 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec
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$exec = S_MOV_B64 7
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...
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# GCN-LABEL: name: vmem_write_exec_expread
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# GCN: BUFFER_LOAD_DWORD_OFFEN
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# GCN-NEXT: V_NOP
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# GCN-NEXT: S_MOV_B64
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---
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name: vmem_write_exec_expread
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body: |
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bb.0:
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $exec_lo, 0, 0, 0, 0, 0, 0, implicit $exec
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$exec = S_MOV_B64 7
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...
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# GCN-LABEL: name: ds_write_m0
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# GCN: DS_READ_B32
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# GCN-NEXT: V_NOP
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# GCN-NEXT: S_MOV_B32
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---
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name: ds_write_m0
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body: |
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bb.0:
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$sgpr4 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = DS_READ_B32 $vgpr0, 0, 0, implicit $m0, implicit $exec
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$m0 = S_MOV_B32 7
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...
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# GCN-LABEL: name: vmem_write_sgpr_fall_through
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# GCN: BUFFER_LOAD_DWORD_OFFEN
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# GCN: V_NOP
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# GCN-NEXT: S_MOV_B32
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---
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name: vmem_write_sgpr_fall_through
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body: |
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bb.0:
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successors: %bb.1
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$sgpr4 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec
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bb.1:
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$sgpr0 = S_MOV_B32 0
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...
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# GCN-LABEL: name: vmem_write_sgpr_branch
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# GCN: BUFFER_LOAD_DWORD_OFFEN
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# GCN-NEXT: S_BRANCH
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# GCN: V_NOP
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# GCN-NEXT: S_MOV_B32
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---
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name: vmem_write_sgpr_branch
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body: |
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bb.0:
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successors: %bb.1
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$sgpr4 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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$sgpr0 = S_MOV_B32 0
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...
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# GCN-LABEL: name: vmem_write_sgpr_branch_around
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# GCN: BUFFER_LOAD_DWORD_OFFEN
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# GCN-NEXT: S_BRANCH
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# GCN: bb.2:
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# GCN-NEXT: V_NOP
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# GCN-NEXT: S_MOV_B32
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---
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name: vmem_write_sgpr_branch_around
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body: |
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bb.0:
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successors: %bb.2
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$sgpr4 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec
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S_BRANCH %bb.2
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bb.1:
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successors: %bb.2
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S_WAITCNT 0
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bb.2:
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$sgpr0 = S_MOV_B32 0
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...
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# GCN-LABEL: name: vmem_write_sgpr_branch_backedge
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# GCN: $vgpr0 = IMPLICIT_DEF
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# GCN-NEXT: V_NOP
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# GCN-NEXT: S_MOV_B32
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---
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name: vmem_write_sgpr_branch_backedge
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body: |
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bb.0:
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successors: %bb.1
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$sgpr4 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$sgpr0 = S_MOV_B32 0
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bb.1:
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec
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S_BRANCH %bb.0
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...
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# GCN-LABEL: name: ds_write_exec
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# GCN: DS_WRITE_B32_gfx9
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# GCN-NEXT: V_NOP
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# GCN-NEXT: S_MOV_B32
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---
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name: ds_write_exec
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body: |
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bb.0:
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = IMPLICIT_DEF
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DS_WRITE_B32_gfx9 $vgpr0, $vgpr1, 0, 0, implicit $exec
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$exec_lo = S_MOV_B32 -1
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...
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