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126 lines
4.0 KiB
LLVM
126 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
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; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
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; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
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; ===================================================================================
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; V_XAD_U32
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; ===================================================================================
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define amdgpu_ps float @xor_add(i32 %a, i32 %b, i32 %c) {
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; VI-LABEL: xor_add:
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; VI: ; %bb.0:
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; VI-NEXT: v_xor_b32_e32 v0, v0, v1
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; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: xor_add:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_xad_u32 v0, v0, v1, v2
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: xor_add:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_xad_u32 v0, v0, v1, v2
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: ; return to shader part epilog
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%x = xor i32 %a, %b
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%result = add i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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; ThreeOp instruction variant not used due to Constant Bus Limitations
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define amdgpu_ps float @xor_add_vgpr_a(i32 %a, i32 inreg %b, i32 inreg %c) {
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; VI-LABEL: xor_add_vgpr_a:
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; VI: ; %bb.0:
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; VI-NEXT: v_xor_b32_e32 v0, s2, v0
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; VI-NEXT: v_add_u32_e32 v0, vcc, s3, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: xor_add_vgpr_a:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0
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; GFX9-NEXT: v_add_u32_e32 v0, s3, v0
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: xor_add_vgpr_a:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_xad_u32 v0, v0, s2, s3
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: ; return to shader part epilog
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%x = xor i32 %a, %b
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%result = add i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @xor_add_vgpr_all(i32 %a, i32 %b, i32 %c) {
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; VI-LABEL: xor_add_vgpr_all:
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; VI: ; %bb.0:
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; VI-NEXT: v_xor_b32_e32 v0, v0, v1
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; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: xor_add_vgpr_all:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_xad_u32 v0, v0, v1, v2
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: xor_add_vgpr_all:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_xad_u32 v0, v0, v1, v2
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: ; return to shader part epilog
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%x = xor i32 %a, %b
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%result = add i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @xor_add_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) {
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; VI-LABEL: xor_add_vgpr_ab:
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; VI: ; %bb.0:
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; VI-NEXT: v_xor_b32_e32 v0, v0, v1
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; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: xor_add_vgpr_ab:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_xad_u32 v0, v0, v1, s2
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: xor_add_vgpr_ab:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_xad_u32 v0, v0, v1, s2
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: ; return to shader part epilog
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%x = xor i32 %a, %b
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%result = add i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @xor_add_vgpr_const(i32 %a, i32 %b) {
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; VI-LABEL: xor_add_vgpr_const:
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; VI: ; %bb.0:
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; VI-NEXT: v_xor_b32_e32 v0, 3, v0
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; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: xor_add_vgpr_const:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_xad_u32 v0, v0, 3, v1
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: xor_add_vgpr_const:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_xad_u32 v0, v0, 3, v1
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: ; return to shader part epilog
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%x = xor i32 %a, 3
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%result = add i32 %x, %b
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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