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llvm-mirror/test/CodeGen/Thumb/branchless-cmp.ll
Alexandros Lamprineas 912039ffa2 [SelectionDAG] swap select_cc operands to enable folding
The DAGCombiner tries to SimplifySelectCC as follows:

  select_cc(x, y, 16, 0, cc) -> shl(zext(set_cc(x, y, cc)), 4)

It can't cope with the situation of reordered operands:

  select_cc(x, y, 0, 16, cc)

In that case we just need to swap the operands and invert the Condition Code:

  select_cc(x, y, 16, 0, ~cc)

Differential Revision: https://reviews.llvm.org/D53236

llvm-svn: 346484
2018-11-09 11:09:40 +00:00

102 lines
2.3 KiB
LLVM

; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m0 %s -verify-machineinstrs -o - | FileCheck %s
define i32 @test1a(i32 %a, i32 %b) {
entry:
%cmp = icmp ne i32 %a, %b
%cond = zext i1 %cmp to i32
ret i32 %cond
; CHECK-LABEL: test1a:
; CHECK-NOT: b{{(ne)|(eq)}}
; CHECK: subs r0, r0, r1
; CHECK-NEXT: subs r1, r0, #1
; CHECK-NEXT: sbcs r0, r1
}
define i32 @test1b(i32 %a, i32 %b) {
entry:
%cmp = icmp eq i32 %a, %b
%cond = zext i1 %cmp to i32
ret i32 %cond
; CHECK-LABEL: test1b:
; CHECK-NOT: b{{(ne)|(eq)}}
; CHECK: subs r1, r0, r1
; CHECK-NEXT: rsbs r0, r1, #0
; CHECK-NEXT: adcs r0, r1
}
define i32 @test2a(i32 %a, i32 %b) {
entry:
%cmp = icmp eq i32 %a, %b
%cond = zext i1 %cmp to i32
ret i32 %cond
; CHECK-LABEL: test2a:
; CHECK-NOT: b{{(ne)|(eq)}}
; CHECK: subs r1, r0, r1
; CHECK-NEXT: rsbs r0, r1, #0
; CHECK-NEXT: adcs r0, r1
}
define i32 @test2b(i32 %a, i32 %b) {
entry:
%cmp = icmp ne i32 %a, %b
%cond = zext i1 %cmp to i32
ret i32 %cond
; CHECK-LABEL: test2b:
; CHECK-NOT: b{{(ne)|(eq)}}
; CHECK: subs r0, r0, r1
; CHECK-NEXT: subs r1, r0, #1
; CHECK-NEXT: sbcs r0, r1
}
define i32 @test3a(i32 %a, i32 %b) {
entry:
%cmp = icmp eq i32 %a, %b
%cond = select i1 %cmp, i32 0, i32 4
ret i32 %cond
; CHECK-LABEL: test3a:
; CHECK-NOT: b{{(ne)|(eq)}}
; CHECK: subs r0, r0, r1
; CHECK-NEXT: subs r1, r0, #1
; CHECK-NEXT: sbcs r0, r1
; CHECK-NEXT: lsls r0, r0, #2
}
define i32 @test3b(i32 %a, i32 %b) {
entry:
%cmp = icmp eq i32 %a, %b
%cond = select i1 %cmp, i32 4, i32 0
ret i32 %cond
; CHECK-LABEL: test3b:
; CHECK-NOT: b{{(ne)|(eq)}}
; CHECK: subs r0, r0, r1
; CHECK-NEXT: rsbs r1, r0, #0
; CHECK-NEXT: adcs r1, r0
; CHECK-NEXT: lsls r0, r1, #2
}
define i32 @test4a(i32 %a, i32 %b) {
entry:
%cmp = icmp ne i32 %a, %b
%cond = select i1 %cmp, i32 0, i32 4
ret i32 %cond
; CHECK-LABEL: test4a:
; CHECK-NOT: b{{(ne)|(eq)}}
; CHECK: subs r0, r0, r1
; CHECK-NEXT: rsbs r1, r0, #0
; CHECK-NEXT: adcs r1, r0
; CHECK-NEXT: lsls r0, r1, #2
}
define i32 @test4b(i32 %a, i32 %b) {
entry:
%cmp = icmp ne i32 %a, %b
%cond = select i1 %cmp, i32 4, i32 0
ret i32 %cond
; CHECK-LABEL: test4b:
; CHECK-NOT: b{{(ne)|(eq)}}
; CHECK: subs r0, r0, r1
; CHECK-NEXT: subs r1, r0, #1
; CHECK-NEXT: sbcs r0, r1
; CHECK-NEXT: lsls r0, r0, #2
}