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300cd7b42b
In some cases, we can rename a store operand, in order to enable pairing of stores. For store pairs, that cannot be merged because the first tored register is defined in between the second store, we try to find suitable rename register. First, we check if we can rename the given register: 1. The first store register must be killed at the store, which means we do not have to rename instructions after the first store. 2. We scan backwards from the first store, to find the definition of the stored register and check all uses in between are renamable. Along they way, we collect the minimal register classes of the uses for overlapping (sub/super)registers. Second, we try to find an available register from the minimal physical register class of the original register. A suitable register must not be 1. defined before FirstMI 2. between the previous definition of the register to rename 3. a callee saved register. We use KILL flags to clear defined registers while scanning from the beginning to the end of the block. This triggers quite often, here are the top changes for MultiSource, SPEC2000, SPEC2006 compiled with -O3 for iOS: Metric: aarch64-ldst-opt.NumPairCreated Program base patch diff test-suite...nch/fourinarow/fourinarow.test 2.00 39.00 1850.0% test-suite...s/ASC_Sequoia/IRSmk/IRSmk.test 46.00 80.00 73.9% test-suite...chmarks/Olden/power/power.test 70.00 96.00 37.1% test-suite...cations/hexxagon/hexxagon.test 29.00 39.00 34.5% test-suite...nchmarks/McCat/05-eks/eks.test 100.00 132.00 32.0% test-suite.../Trimaran/enc-rc4/enc-rc4.test 46.00 59.00 28.3% test-suite...T2006/473.astar/473.astar.test 160.00 200.00 25.0% test-suite.../Trimaran/enc-md5/enc-md5.test 8.00 10.00 25.0% test-suite...telecomm-gsm/telecomm-gsm.test 113.00 139.00 23.0% test-suite...ediabench/gsm/toast/toast.test 113.00 139.00 23.0% test-suite...Source/Benchmarks/sim/sim.test 91.00 111.00 22.0% test-suite...C/CFP2000/179.art/179.art.test 41.00 49.00 19.5% test-suite...peg2/mpeg2dec/mpeg2decode.test 245.00 279.00 13.9% test-suite...marks/Olden/health/health.test 16.00 18.00 12.5% test-suite...ks/Prolangs-C/cdecl/cdecl.test 90.00 101.00 12.2% test-suite...fice-ispell/office-ispell.test 91.00 100.00 9.9% test-suite...oxyApps-C/miniGMG/miniGMG.test 430.00 465.00 8.1% test-suite...lowfish/security-blowfish.test 39.00 42.00 7.7% test-suite.../Applications/spiff/spiff.test 42.00 45.00 7.1% test-suite...arks/mafft/pairlocalalign.test 2473.00 2646.00 7.0% test-suite.../VersaBench/ecbdes/ecbdes.test 29.00 31.00 6.9% test-suite...nch/beamformer/beamformer.test 220.00 235.00 6.8% test-suite...CFP2000/177.mesa/177.mesa.test 2110.00 2252.00 6.7% test-suite...ve-susan/automotive-susan.test 109.00 116.00 6.4% test-suite...s-C/unix-smail/unix-smail.test 65.00 69.00 6.2% test-suite...CI_Purple/SMG2000/smg2000.test 1194.00 1265.00 5.9% test-suite.../Benchmarks/nbench/nbench.test 472.00 500.00 5.9% test-suite...oxyApps-C/miniAMR/miniAMR.test 248.00 262.00 5.6% test-suite...quoia/CrystalMk/CrystalMk.test 18.00 19.00 5.6% test-suite...rks/tramp3d-v4/tramp3d-v4.test 7331.00 7710.00 5.2% test-suite.../Benchmarks/Bullet/bullet.test 5651.00 5938.00 5.1% test-suite...ternal/HMMER/hmmcalibrate.test 750.00 788.00 5.1% test-suite...T2006/456.hmmer/456.hmmer.test 764.00 802.00 5.0% test-suite...ications/JM/ldecod/ldecod.test 1028.00 1079.00 5.0% test-suite...CFP2006/444.namd/444.namd.test 1368.00 1434.00 4.8% test-suite...marks/7zip/7zip-benchmark.test 4471.00 4685.00 4.8% test-suite...6/464.h264ref/464.h264ref.test 3122.00 3271.00 4.8% test-suite...pplications/oggenc/oggenc.test 1497.00 1565.00 4.5% test-suite...T2000/300.twolf/300.twolf.test 742.00 774.00 4.3% test-suite.../Prolangs-C/loader/loader.test 24.00 25.00 4.2% test-suite...0.perlbench/400.perlbench.test 1983.00 2058.00 3.8% test-suite...ications/JM/lencod/lencod.test 4612.00 4785.00 3.8% test-suite...yApps-C++/PENNANT/PENNANT.test 995.00 1032.00 3.7% test-suite...arks/VersaBench/dbms/dbms.test 54.00 56.00 3.7% Reviewers: efriedma, thegameg, samparker, dmgreen, paquette, evandro Reviewed By: paquette Differential Revision: https://reviews.llvm.org/D70450
275 lines
9.3 KiB
LLVM
275 lines
9.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 -mcpu=cyclone -enable-misched=false | FileCheck %s
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; rdar://13625505
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; Here we have 9 fixed integer arguments the 9th argument in on stack, the
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; varargs start right after at 8-byte alignment.
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define void @fn9(i32* %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9, ...) nounwind noinline ssp {
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; CHECK-LABEL: fn9:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: sub sp, sp, #64 ; =64
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; CHECK-NEXT: ldr w8, [sp, #64]
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; CHECK-NEXT: stp w2, w1, [sp, #52]
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; CHECK-NEXT: stp w4, w3, [sp, #44]
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; CHECK-NEXT: stp w6, w5, [sp, #36]
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; CHECK-NEXT: str w7, [sp, #32]
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; CHECK-NEXT: str w8, [x0]
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; CHECK-NEXT: ldr w9, [sp, #72]
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; CHECK-NEXT: ldr w8, [sp, #80]
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; CHECK-NEXT: stp w8, w9, [sp, #16]
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; CHECK-NEXT: add x8, sp, #72 ; =72
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; CHECK-NEXT: add x8, x8, #24 ; =24
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; CHECK-NEXT: str x8, [sp, #24]
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; CHECK-NEXT: ldr w8, [sp, #88]
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; CHECK-NEXT: str w8, [sp, #12]
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; CHECK-NEXT: add sp, sp, #64 ; =64
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; CHECK-NEXT: ret
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%1 = alloca i32, align 4
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%2 = alloca i32, align 4
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%3 = alloca i32, align 4
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%4 = alloca i32, align 4
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%5 = alloca i32, align 4
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%6 = alloca i32, align 4
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%7 = alloca i32, align 4
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%8 = alloca i32, align 4
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%9 = alloca i32, align 4
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%args = alloca i8*, align 8
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%a10 = alloca i32, align 4
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%a11 = alloca i32, align 4
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%a12 = alloca i32, align 4
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store i32 %a2, i32* %2, align 4
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store i32 %a3, i32* %3, align 4
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store i32 %a4, i32* %4, align 4
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store i32 %a5, i32* %5, align 4
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store i32 %a6, i32* %6, align 4
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store i32 %a7, i32* %7, align 4
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store i32 %a8, i32* %8, align 4
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store i32 %a9, i32* %9, align 4
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store i32 %a9, i32* %a1
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%10 = bitcast i8** %args to i8*
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call void @llvm.va_start(i8* %10)
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%11 = va_arg i8** %args, i32
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store i32 %11, i32* %a10, align 4
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%12 = va_arg i8** %args, i32
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store i32 %12, i32* %a11, align 4
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%13 = va_arg i8** %args, i32
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store i32 %13, i32* %a12, align 4
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ret void
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}
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declare void @llvm.va_start(i8*) nounwind
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define i32 @main() nounwind ssp {
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; CHECK-LABEL: main:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: sub sp, sp, #96 ; =96
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; CHECK-NEXT: stp x29, x30, [sp, #80] ; 16-byte Folded Spill
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; CHECK-NEXT: mov w9, #1
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; CHECK-NEXT: mov w8, #2
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; CHECK-NEXT: stp w8, w9, [sp, #72]
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; CHECK-NEXT: mov w9, #3
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; CHECK-NEXT: mov w8, #4
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; CHECK-NEXT: stp w8, w9, [sp, #64]
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; CHECK-NEXT: mov w9, #5
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; CHECK-NEXT: mov w8, #6
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; CHECK-NEXT: stp w8, w9, [sp, #56]
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; CHECK-NEXT: mov w9, #7
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; CHECK-NEXT: mov w8, #8
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; CHECK-NEXT: stp w8, w9, [sp, #48]
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; CHECK-NEXT: mov w8, #9
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; CHECK-NEXT: mov w9, #10
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; CHECK-NEXT: stp w9, w8, [sp, #40]
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; CHECK-NEXT: mov w10, #11
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; CHECK-NEXT: mov w11, #12
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; CHECK-NEXT: stp w11, w10, [sp, #32]
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; CHECK-NEXT: stp x10, x11, [sp, #16]
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; CHECK-NEXT: str x9, [sp, #8]
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; CHECK-NEXT: str w8, [sp]
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; CHECK-NEXT: add x0, sp, #76 ; =76
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; CHECK-NEXT: mov w1, #2
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; CHECK-NEXT: mov w2, #3
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; CHECK-NEXT: mov w3, #4
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; CHECK-NEXT: mov w4, #5
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; CHECK-NEXT: mov w5, #6
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; CHECK-NEXT: mov w6, #7
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; CHECK-NEXT: mov w7, #8
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; CHECK-NEXT: bl _fn9
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; CHECK-NEXT: mov w0, #0
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; CHECK-NEXT: ldp x29, x30, [sp, #80] ; 16-byte Folded Reload
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; CHECK-NEXT: add sp, sp, #96 ; =96
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; CHECK-NEXT: ret
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%a1 = alloca i32, align 4
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%a2 = alloca i32, align 4
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%a3 = alloca i32, align 4
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%a4 = alloca i32, align 4
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%a5 = alloca i32, align 4
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%a6 = alloca i32, align 4
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%a7 = alloca i32, align 4
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%a8 = alloca i32, align 4
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%a9 = alloca i32, align 4
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%a10 = alloca i32, align 4
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%a11 = alloca i32, align 4
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%a12 = alloca i32, align 4
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store i32 1, i32* %a1, align 4
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store i32 2, i32* %a2, align 4
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store i32 3, i32* %a3, align 4
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store i32 4, i32* %a4, align 4
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store i32 5, i32* %a5, align 4
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store i32 6, i32* %a6, align 4
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store i32 7, i32* %a7, align 4
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store i32 8, i32* %a8, align 4
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store i32 9, i32* %a9, align 4
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store i32 10, i32* %a10, align 4
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store i32 11, i32* %a11, align 4
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store i32 12, i32* %a12, align 4
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%1 = load i32, i32* %a1, align 4
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%2 = load i32, i32* %a2, align 4
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%3 = load i32, i32* %a3, align 4
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%4 = load i32, i32* %a4, align 4
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%5 = load i32, i32* %a5, align 4
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%6 = load i32, i32* %a6, align 4
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%7 = load i32, i32* %a7, align 4
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%8 = load i32, i32* %a8, align 4
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%9 = load i32, i32* %a9, align 4
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%10 = load i32, i32* %a10, align 4
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%11 = load i32, i32* %a11, align 4
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%12 = load i32, i32* %a12, align 4
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call void (i32*, i32, i32, i32, i32, i32, i32, i32, i32, ...) @fn9(i32* %a1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12)
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ret i32 0
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}
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;rdar://13668483
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@.str = private unnamed_addr constant [4 x i8] c"fmt\00", align 1
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define void @foo(i8* %fmt, ...) nounwind {
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; CHECK-LABEL: foo:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: sub sp, sp, #48 ; =48
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; CHECK-NEXT: ldr w8, [sp, #48]
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; CHECK-NEXT: str w8, [sp, #28]
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; CHECK-NEXT: add x8, sp, #48 ; =48
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; CHECK-NEXT: add x8, x8, #23 ; =23
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; CHECK-NEXT: and x8, x8, #0xfffffffffffffff0
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; CHECK-NEXT: add x9, x8, #16 ; =16
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; CHECK-NEXT: stp x9, x0, [sp, #32]
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; CHECK-NEXT: ldr q0, [x8]
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; CHECK-NEXT: str q0, [sp], #48
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; CHECK-NEXT: ret
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entry:
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%fmt.addr = alloca i8*, align 8
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%args = alloca i8*, align 8
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%vc = alloca i32, align 4
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%vv = alloca <4 x i32>, align 16
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store i8* %fmt, i8** %fmt.addr, align 8
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%args1 = bitcast i8** %args to i8*
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call void @llvm.va_start(i8* %args1)
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%0 = va_arg i8** %args, i32
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store i32 %0, i32* %vc, align 4
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%1 = va_arg i8** %args, <4 x i32>
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store <4 x i32> %1, <4 x i32>* %vv, align 16
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ret void
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}
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define void @bar(i32 %x, <4 x i32> %y) nounwind {
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; CHECK-LABEL: bar:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: sub sp, sp, #80 ; =80
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; CHECK-NEXT: stp x29, x30, [sp, #64] ; 16-byte Folded Spill
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; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0
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; CHECK-NEXT: str w0, [sp, #60]
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; CHECK-NEXT: stp q0, q0, [sp, #16]
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; CHECK-NEXT: str x0, [sp]
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; CHECK-NEXT: Lloh0:
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; CHECK-NEXT: adrp x0, l_.str@PAGE
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; CHECK-NEXT: Lloh1:
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; CHECK-NEXT: add x0, x0, l_.str@PAGEOFF
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; CHECK-NEXT: bl _foo
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; CHECK-NEXT: ldp x29, x30, [sp, #64] ; 16-byte Folded Reload
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; CHECK-NEXT: add sp, sp, #80 ; =80
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; CHECK-NEXT: ret
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; CHECK-NEXT: .loh AdrpAdd Lloh0, Lloh1
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entry:
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%x.addr = alloca i32, align 4
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%y.addr = alloca <4 x i32>, align 16
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store i32 %x, i32* %x.addr, align 4
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store <4 x i32> %y, <4 x i32>* %y.addr, align 16
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%0 = load i32, i32* %x.addr, align 4
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%1 = load <4 x i32>, <4 x i32>* %y.addr, align 16
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call void (i8*, ...) @foo(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %0, <4 x i32> %1)
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ret void
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}
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; rdar://13668927
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; When passing 16-byte aligned small structs as vararg, make sure the caller
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; side is 16-byte aligned on stack.
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%struct.s41 = type { i32, i16, i32, i16 }
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define void @foo2(i8* %fmt, ...) nounwind {
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; CHECK-LABEL: foo2:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: sub sp, sp, #48 ; =48
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; CHECK-NEXT: ldr w8, [sp, #48]
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; CHECK-NEXT: str w8, [sp, #28]
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; CHECK-NEXT: add x8, sp, #48 ; =48
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; CHECK-NEXT: add x8, x8, #23 ; =23
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; CHECK-NEXT: and x8, x8, #0xfffffffffffffff0
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; CHECK-NEXT: add x9, x8, #16 ; =16
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; CHECK-NEXT: stp x9, x0, [sp, #32]
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; CHECK-NEXT: ldr q0, [x8]
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; CHECK-NEXT: str q0, [sp], #48
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; CHECK-NEXT: ret
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entry:
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%fmt.addr = alloca i8*, align 8
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%args = alloca i8*, align 8
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%vc = alloca i32, align 4
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%vs = alloca %struct.s41, align 16
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store i8* %fmt, i8** %fmt.addr, align 8
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%args1 = bitcast i8** %args to i8*
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call void @llvm.va_start(i8* %args1)
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%0 = va_arg i8** %args, i32
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store i32 %0, i32* %vc, align 4
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%ap.cur = load i8*, i8** %args
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%1 = getelementptr i8, i8* %ap.cur, i32 15
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%2 = ptrtoint i8* %1 to i64
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%3 = and i64 %2, -16
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%ap.align = inttoptr i64 %3 to i8*
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%ap.next = getelementptr i8, i8* %ap.align, i32 16
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store i8* %ap.next, i8** %args
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%4 = bitcast i8* %ap.align to %struct.s41*
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%5 = bitcast %struct.s41* %vs to i8*
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%6 = bitcast %struct.s41* %4 to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %5, i8* align 16 %6, i64 16, i1 false)
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ret void
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}
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind
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define void @bar2(i32 %x, i128 %s41.coerce) nounwind {
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; CHECK-LABEL: bar2:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: sub sp, sp, #80 ; =80
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; CHECK-NEXT: stp x29, x30, [sp, #64] ; 16-byte Folded Spill
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; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0
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; CHECK-NEXT: str w0, [sp, #60]
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; CHECK-NEXT: stp x1, x2, [sp, #32]
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; CHECK-NEXT: stp x1, x2, [sp, #16]
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; CHECK-NEXT: str x0, [sp]
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; CHECK-NEXT: Lloh2:
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; CHECK-NEXT: adrp x0, l_.str@PAGE
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; CHECK-NEXT: Lloh3:
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; CHECK-NEXT: add x0, x0, l_.str@PAGEOFF
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; CHECK-NEXT: bl _foo2
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; CHECK-NEXT: ldp x29, x30, [sp, #64] ; 16-byte Folded Reload
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; CHECK-NEXT: add sp, sp, #80 ; =80
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; CHECK-NEXT: ret
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; CHECK-NEXT: .loh AdrpAdd Lloh2, Lloh3
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entry:
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%x.addr = alloca i32, align 4
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%s41 = alloca %struct.s41, align 16
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store i32 %x, i32* %x.addr, align 4
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%0 = bitcast %struct.s41* %s41 to i128*
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store i128 %s41.coerce, i128* %0, align 1
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%1 = load i32, i32* %x.addr, align 4
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%2 = bitcast %struct.s41* %s41 to i128*
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%3 = load i128, i128* %2, align 1
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call void (i8*, ...) @foo2(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %1, i128 %3)
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ret void
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}
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