1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
llvm-mirror/lib/Target/Hexagon/HexagonIICScalar.td
2020-04-23 14:26:32 +09:00

32 lines
1.3 KiB
TableGen

//===--- HexagonIICScalar.td ----------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
// These itinerary class descriptions are based on the instruction timing
// classes as per V62. Currently, they are just extracted from
// HexagonScheduleV62.td but will soon be auto-generated by HexagonGen.py.
class PseudoItin {
list<InstrItinData> PseudoItin_list = [
InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
[1, 1, 1]>,
InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
];
}
class ScalarItin {
list<InstrItinData> ScalarItin_list = [
InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
[3, 1], [Hex_FWD, Hex_FWD]>,
InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
[1, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>
];
}