mirror of
https://github.com/RPCS3/llvm-mirror.git
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4b2325a925
Note: This version fixed an issue with the TBZ/TBNZ instructions that were generated in FastISel. The issue was that the 64bit version of TBZ (TBZX) automagically sets the upper bit of the immediate field that is used to specify the bit we want to test. To test for any of the lower 32bits we have to first extract the subregister and use the 32bit version of the TBZ instruction (TBZW). Original commit message: Teach selectBranch to fold bit test and branch into a single instruction (TBZ or TBNZ). llvm-svn: 218693
126 lines
2.7 KiB
LLVM
126 lines
2.7 KiB
LLVM
; RUN: llc -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s
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; RUN: llc -fast-isel -fast-isel-abort -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s
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define i32 @icmp_eq_i8(i8 zeroext %a) {
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; CHECK-LABEL: icmp_eq_i8
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; CHECK: tbz {{w[0-9]+}}, #0, {{LBB.+_2}}
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%1 = and i8 %a, 1
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%2 = icmp eq i8 %1, 0
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br i1 %2, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_eq_i16(i16 zeroext %a) {
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; CHECK-LABEL: icmp_eq_i16
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; CHECK: tbz w0, #1, {{LBB.+_2}}
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%1 = and i16 %a, 2
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%2 = icmp eq i16 %1, 0
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br i1 %2, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_eq_i32(i32 %a) {
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; CHECK-LABEL: icmp_eq_i32
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; CHECK: tbz w0, #2, {{LBB.+_2}}
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%1 = and i32 %a, 4
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%2 = icmp eq i32 %1, 0
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br i1 %2, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_eq_i64_1(i64 %a) {
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; CHECK-LABEL: icmp_eq_i64_1
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; CHECK: tbz w0, #3, {{LBB.+_2}}
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%1 = and i64 %a, 8
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%2 = icmp eq i64 %1, 0
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br i1 %2, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_eq_i64_2(i64 %a) {
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; CHECK-LABEL: icmp_eq_i64_2
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; CHECK: tbz x0, #32, {{LBB.+_2}}
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%1 = and i64 %a, 4294967296
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%2 = icmp eq i64 %1, 0
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br i1 %2, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_ne_i8(i8 zeroext %a) {
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; CHECK-LABEL: icmp_ne_i8
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; CHECK: tbnz w0, #0, {{LBB.+_2}}
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%1 = and i8 %a, 1
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%2 = icmp ne i8 %1, 0
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br i1 %2, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_ne_i16(i16 zeroext %a) {
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; CHECK-LABEL: icmp_ne_i16
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; CHECK: tbnz w0, #1, {{LBB.+_2}}
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%1 = and i16 %a, 2
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%2 = icmp ne i16 %1, 0
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br i1 %2, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_ne_i32(i32 %a) {
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; CHECK-LABEL: icmp_ne_i32
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; CHECK: tbnz w0, #2, {{LBB.+_2}}
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%1 = and i32 %a, 4
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%2 = icmp ne i32 %1, 0
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br i1 %2, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_ne_i64_1(i64 %a) {
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; CHECK-LABEL: icmp_ne_i64_1
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; CHECK: tbnz w0, #3, {{LBB.+_2}}
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%1 = and i64 %a, 8
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%2 = icmp ne i64 %1, 0
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br i1 %2, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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define i32 @icmp_ne_i64_2(i64 %a) {
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; CHECK-LABEL: icmp_ne_i64_2
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; CHECK: tbnz x0, #32, {{LBB.+_2}}
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%1 = and i64 %a, 4294967296
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%2 = icmp ne i64 %1, 0
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br i1 %2, label %bb1, label %bb2, !prof !0
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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!0 = metadata !{metadata !"branch_weights", i32 0, i32 2147483647}
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!1 = metadata !{metadata !"branch_weights", i32 2147483647, i32 0}
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