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008347d85e
Summary: The P5600 is an out-of-order, superscalar implementation of the MIPS32R5 architecture. The scheduler has a few missing details (see the 'Tricky Instructions' section and some quirks of the P5600 are deliberately omitted due to implementation difficulty and low chance of significant benefit (e.g. the predicate on P5600WriteEitherALU). However, testing on SingleSource is showing significant performance benefits on some apps (seven in the 10-30% range) and only one significant regression (12%) when -pre-RA-sched=linearize is given. Without -pre-RA-sched=linearize the results are more variable. Some do even better (up to 55% improvement) but increased numbers of copies are slowing others down (up to 12%). Overall, the scheduler as it currently stands is a 2.4% win with -pre-RA-sched=linearize and a 2.7% win without -pre-RA-sched=linearize. I'm sure we can improve on this further. For completeness, the FPGA this was tested on shows some failures with and without the P5600 scheduler. These appear to be scheduling related since the two test runs have fairly different sets of failing tests even after accounting for other factors (e.g. spurious connection failures) however it's not P5600 specific since we also get some for the generic scheduler. Reviewers: vkalintiris Subscribers: mpf, llvm-commits, atrick, vkalintiris Differential Revision: http://reviews.llvm.org/D12193 llvm-svn: 248725
222 lines
11 KiB
TableGen
222 lines
11 KiB
TableGen
//===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This is the top level entry point for the Mips target.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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// The overall idea of the PredicateControl class is to chop the Predicates list
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// into subsets that are usually overridden independently. This allows
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// subclasses to partially override the predicates of their superclasses without
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// having to re-add all the existing predicates.
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class PredicateControl {
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// Predicates for the encoding scheme in use such as HasStdEnc
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list<Predicate> EncodingPredicates = [];
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// Predicates for the GPR size such as IsGP64bit
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list<Predicate> GPRPredicates = [];
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// Predicates for the FGR size and layout such as IsFP64bit
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list<Predicate> FGRPredicates = [];
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// Predicates for the instruction group membership such as ISA's and ASE's
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list<Predicate> InsnPredicates = [];
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// Predicate for marking the instruction as usable in hard-float mode only.
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list<Predicate> HardFloatPredicate = [];
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// Predicates for anything else
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list<Predicate> AdditionalPredicates = [];
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list<Predicate> Predicates = !listconcat(EncodingPredicates,
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GPRPredicates,
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FGRPredicates,
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InsnPredicates,
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HardFloatPredicate,
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AdditionalPredicates);
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}
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// Like Requires<> but for the AdditionalPredicates list
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class AdditionalRequires<list<Predicate> preds> {
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list<Predicate> AdditionalPredicates = preds;
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}
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "MipsRegisterInfo.td"
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include "MipsSchedule.td"
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include "MipsInstrInfo.td"
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include "MipsCallingConv.td"
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def MipsInstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// Mips Subtarget features //
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//===----------------------------------------------------------------------===//
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def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true",
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"Disable SVR4-style position-independent code">;
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def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
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"General Purpose Registers are 64-bit wide">;
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def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
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"Support 64-bit FP registers">;
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def FeatureFPXX : SubtargetFeature<"fpxx", "IsFPXX", "true",
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"Support for FPXX">;
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def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
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"IEEE 754-2008 NaN encoding">;
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def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
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"true", "Only supports single precision float">;
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def FeatureSoftFloat : SubtargetFeature<"soft-float", "IsSoftFloat", "true",
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"Does not support floating point instructions">;
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def FeatureNoOddSPReg : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
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"Disable odd numbered single-precision "
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"registers">;
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def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
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"true", "Enable vector FPU instructions">;
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def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
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"Mips I ISA Support [highly experimental]">;
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def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
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"Mips II ISA Support [highly experimental]",
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[FeatureMips1]>;
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def FeatureMips3_32 : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
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"Subset of MIPS-III that is also in MIPS32 "
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"[highly experimental]">;
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def FeatureMips3_32r2 : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
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"Subset of MIPS-III that is also in MIPS32r2 "
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"[highly experimental]">;
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def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
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"MIPS III ISA Support [highly experimental]",
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[FeatureMips2, FeatureMips3_32,
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FeatureMips3_32r2, FeatureGP64Bit,
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FeatureFP64Bit]>;
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def FeatureMips4_32 : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
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"Subset of MIPS-IV that is also in MIPS32 "
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"[highly experimental]">;
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def FeatureMips4_32r2 : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",
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"Subset of MIPS-IV that is also in MIPS32r2 "
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"[highly experimental]">;
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def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
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"Mips4", "MIPS IV ISA Support",
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[FeatureMips3, FeatureMips4_32,
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FeatureMips4_32r2]>;
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def FeatureMips5_32r2 : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true",
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"Subset of MIPS-V that is also in MIPS32r2 "
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"[highly experimental]">;
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def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
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"MIPS V ISA Support [highly experimental]",
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[FeatureMips4, FeatureMips5_32r2]>;
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def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
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"Mips32 ISA Support",
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[FeatureMips2, FeatureMips3_32,
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FeatureMips4_32]>;
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def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
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"Mips32r2", "Mips32r2 ISA Support",
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[FeatureMips3_32r2, FeatureMips4_32r2,
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FeatureMips5_32r2, FeatureMips32]>;
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def FeatureMips32r3 : SubtargetFeature<"mips32r3", "MipsArchVersion",
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"Mips32r3", "Mips32r3 ISA Support",
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[FeatureMips32r2]>;
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def FeatureMips32r5 : SubtargetFeature<"mips32r5", "MipsArchVersion",
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"Mips32r5", "Mips32r5 ISA Support",
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[FeatureMips32r3]>;
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def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion",
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"Mips32r6",
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"Mips32r6 ISA Support [experimental]",
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[FeatureMips32r5, FeatureFP64Bit,
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FeatureNaN2008]>;
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def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
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"Mips64", "Mips64 ISA Support",
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[FeatureMips5, FeatureMips32]>;
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def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
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"Mips64r2", "Mips64r2 ISA Support",
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[FeatureMips64, FeatureMips32r2]>;
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def FeatureMips64r3 : SubtargetFeature<"mips64r3", "MipsArchVersion",
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"Mips64r3", "Mips64r3 ISA Support",
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[FeatureMips64r2, FeatureMips32r3]>;
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def FeatureMips64r5 : SubtargetFeature<"mips64r5", "MipsArchVersion",
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"Mips64r5", "Mips64r5 ISA Support",
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[FeatureMips64r3, FeatureMips32r5]>;
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def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion",
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"Mips64r6",
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"Mips64r6 ISA Support [experimental]",
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[FeatureMips32r6, FeatureMips64r5,
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FeatureNaN2008]>;
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def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
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"Mips16 mode">;
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def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
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def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
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"Mips DSP-R2 ASE", [FeatureDSP]>;
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def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
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def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">;
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def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
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"microMips mode">;
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def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
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"true", "Octeon cnMIPS Support",
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[FeatureMips64r2]>;
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def FeatureUseTCCInDIV : SubtargetFeature<
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"use-tcc-in-div",
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"UseTCCInDIV", "false",
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"Force the assembler to use trapping">;
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//===----------------------------------------------------------------------===//
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// Mips processors supported.
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//===----------------------------------------------------------------------===//
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def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
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"MipsSubtarget::CPU::P5600",
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"The P5600 Processor", [FeatureMips32r5]>;
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, MipsGenericItineraries, Features>;
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def : Proc<"mips1", [FeatureMips1]>;
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def : Proc<"mips2", [FeatureMips2]>;
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def : Proc<"mips32", [FeatureMips32]>;
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def : Proc<"mips32r2", [FeatureMips32r2]>;
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def : Proc<"mips32r3", [FeatureMips32r3]>;
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def : Proc<"mips32r5", [FeatureMips32r5]>;
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def : Proc<"mips32r6", [FeatureMips32r6]>;
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def : Proc<"mips3", [FeatureMips3]>;
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def : Proc<"mips4", [FeatureMips4]>;
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def : Proc<"mips5", [FeatureMips5]>;
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def : Proc<"mips64", [FeatureMips64]>;
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def : Proc<"mips64r2", [FeatureMips64r2]>;
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def : Proc<"mips64r3", [FeatureMips64r3]>;
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def : Proc<"mips64r5", [FeatureMips64r5]>;
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def : Proc<"mips64r6", [FeatureMips64r6]>;
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def : Proc<"mips16", [FeatureMips16]>;
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def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
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def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
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def MipsAsmParser : AsmParser {
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let ShouldEmitMatchRegisterName = 0;
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let MnemonicContainsDot = 1;
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}
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def MipsAsmParserVariant : AsmParserVariant {
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int Variant = 0;
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// Recognize hard coded registers.
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string RegisterPrefix = "$";
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}
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def Mips : Target {
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let InstructionSet = MipsInstrInfo;
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let AssemblyParsers = [MipsAsmParser];
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let AssemblyParserVariants = [MipsAsmParserVariant];
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}
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