mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-26 22:42:46 +02:00
ead0e16c6e
This patch does the following: * Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`, and isn't `virtual` anymore. This will break out-of-tree targets, silently if they used `virtual` and with a build error if they used `override`. * Factor out `canRealignStack` as a `virtual` function on `TargetRegisterInfo`, by default only looks for the `no-realign-stack` function attribute. Multiple targets duplicated the same `needsStackRealignment` code: - Aarch64. - ARM. - Mips almost: had extra `DEBUG` diagnostic, which the default implementation now has. - PowerPC. - WebAssembly. - x86 almost: has an extra `-force-align-stack` option, which the default implementation now has. The default implementation of `needsStackRealignment` used to just return `false`. My current patch changes the behavior by simply using the above shared behavior. This affects: - AMDGPU - BPF - CppBackend - MSP430 - NVPTX - Sparc - SystemZ - XCore - Out-of-tree targets This is a breaking change! `make check` passes. The only implementation of the `virtual` function (besides the slight different in x86) was Hexagon (which did `MF.getFrameInfo()->getMaxAlignment() > 8`), and potentially some out-of-tree targets. Hexagon now uses the default implementation. `needsStackRealignment` was being overwritten in `<Target>GenRegisterInfo.inc`, to return `false` as the default also did. That was odd and is now gone. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11160 llvm-svn: 242727
81 lines
2.9 KiB
C++
81 lines
2.9 KiB
C++
//===-- MipsRegisterInfo.h - Mips Register Information Impl -----*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the Mips implementation of the TargetRegisterInfo class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H
|
|
#define LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H
|
|
|
|
#include "Mips.h"
|
|
#include "llvm/Target/TargetRegisterInfo.h"
|
|
|
|
#define GET_REGINFO_HEADER
|
|
#include "MipsGenRegisterInfo.inc"
|
|
|
|
namespace llvm {
|
|
class MipsRegisterInfo : public MipsGenRegisterInfo {
|
|
public:
|
|
MipsRegisterInfo();
|
|
|
|
/// getRegisterNumbering - Given the enum value for some register, e.g.
|
|
/// Mips::RA, return the number that it corresponds to (e.g. 31).
|
|
static unsigned getRegisterNumbering(unsigned RegEnum);
|
|
|
|
/// Get PIC indirect call register
|
|
static unsigned getPICCallReg();
|
|
|
|
/// Adjust the Mips stack frame.
|
|
void adjustMipsStackFrame(MachineFunction &MF) const;
|
|
|
|
/// Code Generation virtual methods...
|
|
const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
|
|
unsigned Kind) const override;
|
|
|
|
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
|
|
MachineFunction &MF) const override;
|
|
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
|
|
const uint32_t *getCallPreservedMask(const MachineFunction &MF,
|
|
CallingConv::ID) const override;
|
|
static const uint32_t *getMips16RetHelperMask();
|
|
|
|
BitVector getReservedRegs(const MachineFunction &MF) const override;
|
|
|
|
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
|
|
|
|
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
|
|
|
|
/// Stack Frame Processing Methods
|
|
void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|
int SPAdj, unsigned FIOperandNum,
|
|
RegScavenger *RS = nullptr) const override;
|
|
|
|
void processFunctionBeforeFrameFinalized(MachineFunction &MF,
|
|
RegScavenger *RS = nullptr) const;
|
|
|
|
// Stack realignment queries.
|
|
bool canRealignStack(const MachineFunction &MF) const override;
|
|
|
|
/// Debug information queries.
|
|
unsigned getFrameRegister(const MachineFunction &MF) const override;
|
|
|
|
/// \brief Return GPR register class.
|
|
virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
|
|
|
|
private:
|
|
virtual void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
|
|
int FrameIndex, uint64_t StackSize,
|
|
int64_t SPOffset) const = 0;
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif
|