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51b37329c1
Summary: This includes a hazard recognizer implementation to replace some of the hazard handling we had during frame index elimination. Reviewers: arsenm Subscribers: qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18602 llvm-svn: 268143
44 lines
1.7 KiB
LLVM
44 lines
1.7 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s
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declare float @llvm.amdgcn.rsq.clamp.f32(float) #1
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declare double @llvm.amdgcn.rsq.clamp.f64(double) #1
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; FUNC-LABEL: {{^}}rsq_clamp_f32:
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; SI: v_rsq_clamp_f32_e32
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; VI: s_load_dword [[SRC:s[0-9]+]]
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; VI-DAG: v_rsq_f32_e32 [[RSQ:v[0-9]+]], [[SRC]]
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; VI-DAG: v_min_f32_e32 [[MIN:v[0-9]+]], 0x7f7fffff, [[RSQ]]
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; TODO: this constant should be folded:
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; VI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0xff7fffff
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; VI: v_max_f32_e32 [[RESULT:v[0-9]+]], [[MIN]], [[K]]
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; VI: buffer_store_dword [[RESULT]]
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define void @rsq_clamp_f32(float addrspace(1)* %out, float %src) #0 {
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%rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float %src)
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store float %rsq_clamp, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}rsq_clamp_f64:
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; SI: v_rsq_clamp_f64_e32
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; TODO: this constant should be folded:
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; VI-DAG: s_mov_b32 s[[ALLBITS:[0-9+]]], -1
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; VI-DAG: s_mov_b32 s[[HIGH1:[0-9+]]], 0x7fefffff
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; VI-DAG: s_mov_b32 s[[HIGH2:[0-9+]]], 0xffefffff
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; VI-DAG: s_mov_b32 s[[LOW1:[0-9+]]], s[[ALLBITS]]
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; VI-DAG: v_rsq_f64_e32 [[RSQ:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}}
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; VI: s_mov_b32 s[[LOW2:[0-9+]]], s[[ALLBITS]]
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; VI: v_min_f64 v[0:1], [[RSQ]], s{{\[}}[[LOW1]]:[[HIGH1]]]
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; VI: v_max_f64 v[0:1], v[0:1], s{{\[}}[[LOW2]]:[[HIGH2]]]
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define void @rsq_clamp_f64(double addrspace(1)* %out, double %src) #0 {
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%rsq_clamp = call double @llvm.amdgcn.rsq.clamp.f64(double %src)
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store double %rsq_clamp, double addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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