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50 lines
2.0 KiB
TableGen
50 lines
2.0 KiB
TableGen
//WebAssemblyRegisterInfo.td-Describe the WebAssembly Registers -*- tablegen -*-
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This file describes the WebAssembly register classes and some nominal
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/// physical registers.
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///
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//===----------------------------------------------------------------------===//
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class WebAssemblyReg<string n> : Register<n> {
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let Namespace = "WebAssembly";
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}
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class WebAssemblyRegClass<list<ValueType> regTypes, int alignment, dag regList>
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: RegisterClass<"WebAssembly", regTypes, alignment, regList>;
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//===----------------------------------------------------------------------===//
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// Registers
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//===----------------------------------------------------------------------===//
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// Special registers used as the frame and stack pointer.
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//
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// WebAssembly may someday supports mixed 32-bit and 64-bit heaps in the same
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// application, which requires separate width FP and SP.
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def FP32 : WebAssemblyReg<"%FP32">;
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def FP64 : WebAssemblyReg<"%FP64">;
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def SP32 : WebAssemblyReg<"%SP32">;
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def SP64 : WebAssemblyReg<"%SP64">;
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// The register allocation framework requires register classes have at least
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// one register, so we define a few for the floating point register classes
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// since we otherwise don't need a physical register in those classes.
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def F32_0 : WebAssemblyReg<"%f32.0">;
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def F64_0 : WebAssemblyReg<"%f64.0">;
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//===----------------------------------------------------------------------===//
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// Register classes
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//===----------------------------------------------------------------------===//
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def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32)>;
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def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64)>;
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def F32 : WebAssemblyRegClass<[f32], 32, (add F32_0)>;
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def F64 : WebAssemblyRegClass<[f64], 64, (add F64_0)>;
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