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6017c1a2f3
This teaches GISel to select patterns which fold an extend plus optional shift into the addressing mode. In particular, adds and subs. Factor out the arith extended register ComplexPatterns in AArch64InstrFormats.td and create GISel equivalents. Add some equivalent functions to the ones in AArch64ISelDAGToDAG: - `selectArithExtendedRegister` - `narrowExtendRegIfNeeded` - `getExtendTypeForInst` `getExtendTypeForInst` includes the checks for loads and stores. This will be used for WRO addressing modes in loads + stores. Teach selectCopy to properly handle subregister copies on the same bank in order to support `narrowExtendRegIfNeeded`. The extended register must be a GPR32, so we need to support same-bank subregister copies. Fix a bug in getSubRegForClass which would cause registers on things like GPR32common to end up getting ssub. Just change the check to look for FPR32 rather than GPR32. For tests: - Add select-arith-extended-reg.mir - Update addsub_ext.ll to include GlobalISel checks Differential Revision: https://reviews.llvm.org/D66835 llvm-svn: 370410
476 lines
16 KiB
LLVM
476 lines
16 KiB
LLVM
; RUN: llc -enable-machine-outliner=never -verify-machineinstrs %s -o - -mtriple=aarch64-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
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; RUN: llc -global-isel -enable-machine-outliner=never -verify-machineinstrs %s -o - -mtriple=aarch64-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s --check-prefix=GISEL
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; FIXME: GISel only knows how to handle explicit G_SEXT instructions. So when
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; G_SEXT is lowered to anything else, it won't fold in a stx*.
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; FIXME: GISel doesn't currently handle folding the addressing mode into a cmp.
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@var8 = global i8 0
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@var16 = global i16 0
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@var32 = global i32 0
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@var64 = global i64 0
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define void @addsub_i8rhs() minsize {
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; CHECK-LABEL: addsub_i8rhs:
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; GISEL-LABEL: addsub_i8rhs:
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%val8_tmp = load i8, i8* @var8
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%lhs32 = load i32, i32* @var32
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%lhs64 = load i64, i64* @var64
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; Need this to prevent extension upon load and give a vanilla i8 operand.
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%val8 = add i8 %val8_tmp, 123
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; Zero-extending to 32-bits
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%rhs32_zext = zext i8 %val8 to i32
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%res32_zext = add i32 %lhs32, %rhs32_zext
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store volatile i32 %res32_zext, i32* @var32
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; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb
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; GISEL: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb
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%rhs32_zext_shift = shl i32 %rhs32_zext, 3
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%res32_zext_shift = add i32 %lhs32, %rhs32_zext_shift
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store volatile i32 %res32_zext_shift, i32* @var32
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; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb #3
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; GISEL: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb #3
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; Zero-extending to 64-bits
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%rhs64_zext = zext i8 %val8 to i64
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%res64_zext = add i64 %lhs64, %rhs64_zext
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store volatile i64 %res64_zext, i64* @var64
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb
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; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb
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%rhs64_zext_shift = shl i64 %rhs64_zext, 1
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%res64_zext_shift = add i64 %lhs64, %rhs64_zext_shift
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store volatile i64 %res64_zext_shift, i64* @var64
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb #1
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; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb #1
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; Sign-extending to 32-bits
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%rhs32_sext = sext i8 %val8 to i32
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%res32_sext = add i32 %lhs32, %rhs32_sext
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store volatile i32 %res32_sext, i32* @var32
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; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb
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%rhs32_sext_shift = shl i32 %rhs32_sext, 1
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%res32_sext_shift = add i32 %lhs32, %rhs32_sext_shift
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store volatile i32 %res32_sext_shift, i32* @var32
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; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb #1
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; Sign-extending to 64-bits
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%rhs64_sext = sext i8 %val8 to i64
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%res64_sext = add i64 %lhs64, %rhs64_sext
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store volatile i64 %res64_sext, i64* @var64
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb
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%rhs64_sext_shift = shl i64 %rhs64_sext, 4
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%res64_sext_shift = add i64 %lhs64, %rhs64_sext_shift
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store volatile i64 %res64_sext_shift, i64* @var64
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb #4
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; CMP variants
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%tst = icmp slt i32 %lhs32, %rhs32_zext
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br i1 %tst, label %end, label %test2
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; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, uxtb
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test2:
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%cmp_sext = sext i8 %val8 to i64
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%tst2 = icmp eq i64 %lhs64, %cmp_sext
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br i1 %tst2, label %other, label %end
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; CHECK: cmp {{x[0-9]+}}, {{w[0-9]+}}, sxtb
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other:
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store volatile i32 %lhs32, i32* @var32
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ret void
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end:
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ret void
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}
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define void @sub_i8rhs() minsize {
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; CHECK-LABEL: sub_i8rhs:
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%val8_tmp = load i8, i8* @var8
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%lhs32 = load i32, i32* @var32
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%lhs64 = load i64, i64* @var64
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; Need this to prevent extension upon load and give a vanilla i8 operand.
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%val8 = add i8 %val8_tmp, 123
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; Zero-extending to 32-bits
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%rhs32_zext = zext i8 %val8 to i32
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%res32_zext = sub i32 %lhs32, %rhs32_zext
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store volatile i32 %res32_zext, i32* @var32
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; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb
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; GISEL: subs {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb
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%rhs32_zext_shift = shl i32 %rhs32_zext, 3
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%res32_zext_shift = sub i32 %lhs32, %rhs32_zext_shift
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store volatile i32 %res32_zext_shift, i32* @var32
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; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb #3
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; GISEL: subs {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb #3
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; Zero-extending to 64-bits
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%rhs64_zext = zext i8 %val8 to i64
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%res64_zext = sub i64 %lhs64, %rhs64_zext
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store volatile i64 %res64_zext, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb
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; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb
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%rhs64_zext_shift = shl i64 %rhs64_zext, 1
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%res64_zext_shift = sub i64 %lhs64, %rhs64_zext_shift
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store volatile i64 %res64_zext_shift, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb #1
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; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb #1
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; Sign-extending to 32-bits
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%rhs32_sext = sext i8 %val8 to i32
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%res32_sext = sub i32 %lhs32, %rhs32_sext
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store volatile i32 %res32_sext, i32* @var32
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; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb
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%rhs32_sext_shift = shl i32 %rhs32_sext, 1
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%res32_sext_shift = sub i32 %lhs32, %rhs32_sext_shift
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store volatile i32 %res32_sext_shift, i32* @var32
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; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb #1
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; Sign-extending to 64-bits
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%rhs64_sext = sext i8 %val8 to i64
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%res64_sext = sub i64 %lhs64, %rhs64_sext
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store volatile i64 %res64_sext, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb
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%rhs64_sext_shift = shl i64 %rhs64_sext, 4
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%res64_sext_shift = sub i64 %lhs64, %rhs64_sext_shift
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store volatile i64 %res64_sext_shift, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb #4
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ret void
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}
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define void @addsub_i16rhs() minsize {
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; CHECK-LABEL: addsub_i16rhs:
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; GISEL-LABEL: addsub_i16rhs:
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%val16_tmp = load i16, i16* @var16
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%lhs32 = load i32, i32* @var32
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%lhs64 = load i64, i64* @var64
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; Need this to prevent extension upon load and give a vanilla i16 operand.
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%val16 = add i16 %val16_tmp, 123
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; Zero-extending to 32-bits
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%rhs32_zext = zext i16 %val16 to i32
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%res32_zext = add i32 %lhs32, %rhs32_zext
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store volatile i32 %res32_zext, i32* @var32
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; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth
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; GISEL: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth
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%rhs32_zext_shift = shl i32 %rhs32_zext, 3
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%res32_zext_shift = add i32 %lhs32, %rhs32_zext_shift
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store volatile i32 %res32_zext_shift, i32* @var32
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; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3
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; GISEL: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3
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; Zero-extending to 64-bits
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%rhs64_zext = zext i16 %val16 to i64
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%res64_zext = add i64 %lhs64, %rhs64_zext
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store volatile i64 %res64_zext, i64* @var64
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth
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; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth
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%rhs64_zext_shift = shl i64 %rhs64_zext, 1
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%res64_zext_shift = add i64 %lhs64, %rhs64_zext_shift
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store volatile i64 %res64_zext_shift, i64* @var64
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1
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; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1
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; Sign-extending to 32-bits
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%rhs32_sext = sext i16 %val16 to i32
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%res32_sext = add i32 %lhs32, %rhs32_sext
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store volatile i32 %res32_sext, i32* @var32
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; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth
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%rhs32_sext_shift = shl i32 %rhs32_sext, 1
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%res32_sext_shift = add i32 %lhs32, %rhs32_sext_shift
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store volatile i32 %res32_sext_shift, i32* @var32
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; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth #1
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; Sign-extending to 64-bits
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%rhs64_sext = sext i16 %val16 to i64
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%res64_sext = add i64 %lhs64, %rhs64_sext
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store volatile i64 %res64_sext, i64* @var64
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxth
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%rhs64_sext_shift = shl i64 %rhs64_sext, 4
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%res64_sext_shift = add i64 %lhs64, %rhs64_sext_shift
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store volatile i64 %res64_sext_shift, i64* @var64
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxth #4
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; CMP variants
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%tst = icmp slt i32 %lhs32, %rhs32_zext
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br i1 %tst, label %end, label %test2
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; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, uxth
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test2:
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%cmp_sext = sext i16 %val16 to i64
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%tst2 = icmp eq i64 %lhs64, %cmp_sext
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br i1 %tst2, label %other, label %end
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; CHECK: cmp {{x[0-9]+}}, {{w[0-9]+}}, sxth
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other:
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store volatile i32 %lhs32, i32* @var32
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ret void
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end:
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ret void
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}
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define void @sub_i16rhs() minsize {
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; CHECK-LABEL: sub_i16rhs:
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; GISEL-LABEL: sub_i16rhs:
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%val16_tmp = load i16, i16* @var16
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%lhs32 = load i32, i32* @var32
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%lhs64 = load i64, i64* @var64
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; Need this to prevent extension upon load and give a vanilla i16 operand.
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%val16 = add i16 %val16_tmp, 123
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; Zero-extending to 32-bits
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%rhs32_zext = zext i16 %val16 to i32
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%res32_zext = sub i32 %lhs32, %rhs32_zext
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store volatile i32 %res32_zext, i32* @var32
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; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth
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; GISEL: subs {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth
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%rhs32_zext_shift = shl i32 %rhs32_zext, 3
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%res32_zext_shift = sub i32 %lhs32, %rhs32_zext_shift
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store volatile i32 %res32_zext_shift, i32* @var32
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; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3
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; GISEL: subs {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3
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; Zero-extending to 64-bits
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%rhs64_zext = zext i16 %val16 to i64
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%res64_zext = sub i64 %lhs64, %rhs64_zext
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store volatile i64 %res64_zext, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth
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; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth
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%rhs64_zext_shift = shl i64 %rhs64_zext, 1
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%res64_zext_shift = sub i64 %lhs64, %rhs64_zext_shift
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store volatile i64 %res64_zext_shift, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1
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; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1
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; Sign-extending to 32-bits
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%rhs32_sext = sext i16 %val16 to i32
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%res32_sext = sub i32 %lhs32, %rhs32_sext
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store volatile i32 %res32_sext, i32* @var32
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; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth
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%rhs32_sext_shift = shl i32 %rhs32_sext, 1
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%res32_sext_shift = sub i32 %lhs32, %rhs32_sext_shift
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store volatile i32 %res32_sext_shift, i32* @var32
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; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth #1
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; Sign-extending to 64-bits
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%rhs64_sext = sext i16 %val16 to i64
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%res64_sext = sub i64 %lhs64, %rhs64_sext
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store volatile i64 %res64_sext, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxth
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%rhs64_sext_shift = shl i64 %rhs64_sext, 4
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%res64_sext_shift = sub i64 %lhs64, %rhs64_sext_shift
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store volatile i64 %res64_sext_shift, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxth #4
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ret void
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}
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; N.b. we could probably check more here ("add w2, w3, w1, uxtw" for
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; example), but the remaining instructions are probably not idiomatic
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; in the face of "add/sub (shifted register)" so I don't intend to.
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define void @addsub_i32rhs(i32 %in32) minsize {
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; CHECK-LABEL: addsub_i32rhs:
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; GISEL-LABEL: addsub_i32rhs:
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%val32_tmp = load i32, i32* @var32
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%lhs64 = load i64, i64* @var64
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%val32 = add i32 %val32_tmp, 123
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%rhs64_zext = zext i32 %in32 to i64
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%res64_zext = add i64 %lhs64, %rhs64_zext
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store volatile i64 %res64_zext, i64* @var64
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw
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; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw
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%rhs64_zext2 = zext i32 %val32 to i64
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%rhs64_zext_shift = shl i64 %rhs64_zext2, 2
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%res64_zext_shift = add i64 %lhs64, %rhs64_zext_shift
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store volatile i64 %res64_zext_shift, i64* @var64
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw #2
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; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw #2
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%rhs64_sext = sext i32 %val32 to i64
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%res64_sext = add i64 %lhs64, %rhs64_sext
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store volatile i64 %res64_sext, i64* @var64
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw
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; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw
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%rhs64_sext_shift = shl i64 %rhs64_sext, 2
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%res64_sext_shift = add i64 %lhs64, %rhs64_sext_shift
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store volatile i64 %res64_sext_shift, i64* @var64
|
|
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw #2
|
|
; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw #2
|
|
|
|
ret void
|
|
}
|
|
|
|
define void @sub_i32rhs(i32 %in32) minsize {
|
|
; CHECK-LABEL: sub_i32rhs:
|
|
%val32_tmp = load i32, i32* @var32
|
|
%lhs64 = load i64, i64* @var64
|
|
|
|
%val32 = add i32 %val32_tmp, 123
|
|
|
|
%rhs64_zext = zext i32 %in32 to i64
|
|
%res64_zext = sub i64 %lhs64, %rhs64_zext
|
|
store volatile i64 %res64_zext, i64* @var64
|
|
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw
|
|
; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw
|
|
|
|
%rhs64_zext2 = zext i32 %val32 to i64
|
|
%rhs64_zext_shift = shl i64 %rhs64_zext2, 2
|
|
%res64_zext_shift = sub i64 %lhs64, %rhs64_zext_shift
|
|
store volatile i64 %res64_zext_shift, i64* @var64
|
|
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw #2
|
|
; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw #2
|
|
|
|
%rhs64_sext = sext i32 %val32 to i64
|
|
%res64_sext = sub i64 %lhs64, %rhs64_sext
|
|
store volatile i64 %res64_sext, i64* @var64
|
|
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw
|
|
|
|
%rhs64_sext_shift = shl i64 %rhs64_sext, 2
|
|
%res64_sext_shift = sub i64 %lhs64, %rhs64_sext_shift
|
|
store volatile i64 %res64_sext_shift, i64* @var64
|
|
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw #2
|
|
|
|
ret void
|
|
}
|
|
|
|
; Check that implicit zext from w reg write is used instead of uxtw form of add.
|
|
define i64 @add_fold_uxtw(i32 %x, i64 %y) {
|
|
; CHECK-LABEL: add_fold_uxtw:
|
|
; GISEL-LABEL: add_fold_uxtw:
|
|
entry:
|
|
; CHECK: and w[[TMP:[0-9]+]], w0, #0x3
|
|
; GISEL: and w[[TMP:[0-9]+]], w0, #0x3
|
|
; FIXME: Global ISel produces an unncessary ubfx here.
|
|
%m = and i32 %x, 3
|
|
%ext = zext i32 %m to i64
|
|
; CHECK-NEXT: add x0, x1, x[[TMP]]
|
|
; GISEL: add x0, x1, x[[TMP]]
|
|
%ret = add i64 %y, %ext
|
|
ret i64 %ret
|
|
}
|
|
|
|
; Check that implicit zext from w reg write is used instead of uxtw
|
|
; form of sub and that mov WZR is folded to form a neg instruction.
|
|
define i64 @sub_fold_uxtw_xzr(i32 %x) {
|
|
; CHECK-LABEL: sub_fold_uxtw_xzr:
|
|
; GISEL-LABEL: sub_fold_uxtw_xzr:
|
|
entry:
|
|
; CHECK: and w[[TMP:[0-9]+]], w0, #0x3
|
|
; GISEL: and w[[TMP:[0-9]+]], w0, #0x3
|
|
%m = and i32 %x, 3
|
|
%ext = zext i32 %m to i64
|
|
; CHECK-NEXT: neg x0, x[[TMP]]
|
|
; GISEL: negs x0, x[[TMP]]
|
|
%ret = sub i64 0, %ext
|
|
ret i64 %ret
|
|
}
|
|
|
|
; Check that implicit zext from w reg write is used instead of uxtw form of subs/cmp.
|
|
define i1 @cmp_fold_uxtw(i32 %x, i64 %y) {
|
|
; CHECK-LABEL: cmp_fold_uxtw:
|
|
entry:
|
|
; CHECK: and w[[TMP:[0-9]+]], w0, #0x3
|
|
%m = and i32 %x, 3
|
|
%ext = zext i32 %m to i64
|
|
; CHECK-NEXT: cmp x1, x[[TMP]]
|
|
; CHECK-NEXT: cset
|
|
%ret = icmp eq i64 %y, %ext
|
|
ret i1 %ret
|
|
}
|
|
|
|
; Check that implicit zext from w reg write is used instead of uxtw
|
|
; form of add, leading to madd selection.
|
|
define i64 @madd_fold_uxtw(i32 %x, i64 %y) {
|
|
; CHECK-LABEL: madd_fold_uxtw:
|
|
; GISEL-LABEL: madd_fold_uxtw:
|
|
entry:
|
|
; CHECK: and w[[TMP:[0-9]+]], w0, #0x3
|
|
; GISEL: and w[[TMP:[0-9]+]], w0, #0x3
|
|
%m = and i32 %x, 3
|
|
%ext = zext i32 %m to i64
|
|
; GISEL: madd x0, x1, x1, x[[TMP]]
|
|
; CHECK-NEXT: madd x0, x1, x1, x[[TMP]]
|
|
%mul = mul i64 %y, %y
|
|
%ret = add i64 %mul, %ext
|
|
ret i64 %ret
|
|
}
|
|
|
|
; Check that implicit zext from w reg write is used instead of uxtw
|
|
; form of sub, leading to sub/cmp folding.
|
|
; Check that implicit zext from w reg write is used instead of uxtw form of subs/cmp.
|
|
define i1 @cmp_sub_fold_uxtw(i32 %x, i64 %y, i64 %z) {
|
|
; CHECK-LABEL: cmp_sub_fold_uxtw:
|
|
entry:
|
|
; CHECK: and w[[TMP:[0-9]+]], w0, #0x3
|
|
%m = and i32 %x, 3
|
|
%ext = zext i32 %m to i64
|
|
; CHECK-NEXT: cmp x[[TMP2:[0-9]+]], x[[TMP]]
|
|
; CHECK-NEXT: cset
|
|
%sub = sub i64 %z, %ext
|
|
%ret = icmp eq i64 %sub, 0
|
|
ret i1 %ret
|
|
}
|
|
|
|
; Check that implicit zext from w reg write is used instead of uxtw
|
|
; form of add and add of -1 gets selected as sub.
|
|
define i64 @add_imm_fold_uxtw(i32 %x) {
|
|
; CHECK-LABEL: add_imm_fold_uxtw:
|
|
; GISEL-LABEL: add_imm_fold_uxtw:
|
|
entry:
|
|
; CHECK: and w[[TMP:[0-9]+]], w0, #0x3
|
|
; GISEL: and w[[TMP:[0-9]+]], w0, #0x3
|
|
%m = and i32 %x, 3
|
|
%ext = zext i32 %m to i64
|
|
; CHECK-NEXT: sub x0, x[[TMP]], #1
|
|
; GISEL: subs x0, x[[TMP]], #1
|
|
%ret = add i64 %ext, -1
|
|
ret i64 %ret
|
|
}
|
|
|
|
; Check that implicit zext from w reg write is used instead of uxtw
|
|
; form of add and add lsl form gets selected.
|
|
define i64 @add_lsl_fold_uxtw(i32 %x, i64 %y) {
|
|
; CHECK-LABEL: add_lsl_fold_uxtw:
|
|
; GISEL-LABEL: add_lsl_fold_uxtw:
|
|
entry:
|
|
; CHECK: orr w[[TMP:[0-9]+]], w0, #0x3
|
|
; GISEL: orr w[[TMP:[0-9]+]], w0, #0x3
|
|
%m = or i32 %x, 3
|
|
%ext = zext i32 %m to i64
|
|
%shift = shl i64 %y, 3
|
|
; CHECK-NEXT: add x0, x[[TMP]], x1, lsl #3
|
|
; GISEL: add x0, x[[TMP]], x1, lsl #3
|
|
%ret = add i64 %ext, %shift
|
|
ret i64 %ret
|
|
}
|