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b5c44abcf5
Added subtarget features for AArch64 to use TPIDR_EL[1|2|3] as the TLS base register, rather than the default TPIDR_EL0. Patch by Philip Derrin! Differential revision: https://reviews.llvm.org/D54685 llvm-svn: 356657
25 lines
1008 B
LLVM
25 lines
1008 B
LLVM
; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
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; RUN: llc < %s -mtriple=aarch64-fuchsia | FileCheck %s
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; RUN: llc < %s -mtriple=aarch64-fuchsia -code-model=kernel | FileCheck --check-prefix=FUCHSIA-KERNEL %s
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+tpidr-el1 | FileCheck --check-prefix=USEEL1 %s
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+tpidr-el2 | FileCheck --check-prefix=USEEL2 %s
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+tpidr-el3 | FileCheck --check-prefix=USEEL3 %s
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; Function Attrs: nounwind readnone
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declare i8* @llvm.thread.pointer() #1
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define i8* @thread_pointer() {
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; CHECK: thread_pointer:
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; CHECK: mrs {{x[0-9]+}}, TPIDR_EL0
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; FUCHSIA-KERNEL: thread_pointer:
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; FUCHSIA-KERNEL: mrs {{x[0-9]+}}, TPIDR_EL1
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; USEEL1: thread_pointer:
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; USEEL1: mrs {{x[0-9]+}}, TPIDR_EL1
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; USEEL2: thread_pointer:
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; USEEL2: mrs {{x[0-9]+}}, TPIDR_EL2
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; USEEL3: thread_pointer:
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; USEEL3: mrs {{x[0-9]+}}, TPIDR_EL3
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%1 = tail call i8* @llvm.thread.pointer()
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ret i8* %1
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}
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