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1bb14916f2
This is the main CodeGen patch to support the arm64_32 watchOS ABI in LLVM. FastISel is mostly disabled for now since it would generate incorrect code for ILP32. llvm-svn: 371722
49 lines
1.6 KiB
LLVM
49 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu | FileCheck %s --check-prefixes=AARCH
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define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
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; AARCH-LABEL: muloti_test:
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; AARCH: // %bb.0: // %start
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; AARCH-NEXT: mul x8, x3, x0
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; AARCH-NEXT: umulh x9, x0, x2
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; AARCH-NEXT: madd x11, x1, x2, x8
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; AARCH-NEXT: add x8, x9, x11
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; AARCH-NEXT: cmp x8, x9
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; AARCH-NEXT: cset w9, lo
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; AARCH-NEXT: cmp x11, #0 // =0
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; AARCH-NEXT: csel w9, wzr, w9, eq
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; AARCH-NEXT: cmp x3, #0 // =0
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; AARCH-NEXT: umulh x10, x1, x2
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; AARCH-NEXT: cset w12, ne
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; AARCH-NEXT: cmp x1, #0 // =0
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; AARCH-NEXT: umulh x11, x3, x0
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; AARCH-NEXT: cset w13, ne
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; AARCH-NEXT: cmp xzr, x10
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; AARCH-NEXT: and w10, w13, w12
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; AARCH-NEXT: cset w12, ne
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; AARCH-NEXT: cmp xzr, x11
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; AARCH-NEXT: orr w10, w10, w12
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; AARCH-NEXT: cset w11, ne
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; AARCH-NEXT: orr w10, w10, w11
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; AARCH-NEXT: orr w9, w10, w9
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; AARCH-NEXT: mul x0, x0, x2
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; AARCH-DAG: mov x1, x8
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; AARCH-DAG: mov w2, w9
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; AARCH-NEXT: ret
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start:
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%0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
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%1 = extractvalue { i128, i1 } %0, 0
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%2 = extractvalue { i128, i1 } %0, 1
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%3 = zext i1 %2 to i8
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%4 = insertvalue { i128, i8 } undef, i128 %1, 0
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%5 = insertvalue { i128, i8 } %4, i8 %3, 1
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ret { i128, i8 } %5
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}
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; Function Attrs: nounwind readnone speculatable
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declare { i128, i1 } @llvm.umul.with.overflow.i128(i128, i128) #1
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attributes #0 = { nounwind readnone uwtable }
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attributes #1 = { nounwind readnone speculatable }
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attributes #2 = { nounwind }
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