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0663a19f9d
The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
35 lines
1.6 KiB
LLVM
35 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 | FileCheck %s
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; ModuleID = '<stdin>'
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-darwin11.2.0"
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; During legalization, the vselect mask is 'type legalized' into a
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; wider BUILD_VECTOR. This causes the introduction of a new
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; sign_extend_inreg in the DAG.
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;
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; A sign_extend_inreg of a vector of ConstantSDNode or undef can be
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; always folded into a simple build_vector.
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;
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; Make sure that the sign_extend_inreg is simplified and that we
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; don't generate psll, psraw and pblendvb from the vselect.
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define void @foo8(float* nocapture %RET) nounwind {
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; CHECK-LABEL: foo8:
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; CHECK: ## %bb.0: ## %allocas
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; CHECK-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
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; CHECK-NEXT: cvtdq2ps %xmm0, %xmm0
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; CHECK-NEXT: movaps {{.*#+}} xmm1 = [1.0E+2,2.0E+0,1.0E+2,4.0E+0]
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; CHECK-NEXT: movups %xmm1, (%rdi)
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; CHECK-NEXT: movups %xmm0, 16(%rdi)
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; CHECK-NEXT: retq
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allocas:
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%resultvec.i = select <8 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <8 x i8> <i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100>
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%uint2float = uitofp <8 x i8> %resultvec.i to <8 x float>
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%ptr = bitcast float * %RET to <8 x float> *
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store <8 x float> %uint2float, <8 x float>* %ptr, align 4
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ret void
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}
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