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FP128 values are passed in xmm registers so should be asssociated with an SSE feature rather than MMX which uses a different set of registers. llc enables sse1 and sse2 by default with x86_64. But does not enable mmx. Clang enables all 3 features by default. I've tried to add command lines to test with -sse where possible, but any test that returns a value in an xmm register fails with a fatal error with -sse since we have no defined ABI for that scenario. llvm-svn: 370682
52 lines
1.9 KiB
LLVM
52 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-macosx10.9 -verify-machineinstrs -mattr=cx16 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-macosx10.9 -verify-machineinstrs -mattr=cx16 -mattr=-sse | FileCheck %s --check-prefix=NOSSE
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; FIXME: This test has a fatal error in 32-bit mode
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@fsc128 = external global fp128
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define void @atomic_fetch_swapf128(fp128 %x) nounwind {
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; CHECK-LABEL: atomic_fetch_swapf128:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: movq _fsc128@{{.*}}(%rip), %rsi
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; CHECK-NEXT: movaps (%rsi), %xmm1
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB0_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rbx
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; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
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; CHECK-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax
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; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rdx
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; CHECK-NEXT: lock cmpxchg16b (%rsi)
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; CHECK-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm1
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; CHECK-NEXT: jne LBB0_1
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; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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;
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; NOSSE-LABEL: atomic_fetch_swapf128:
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; NOSSE: ## %bb.0:
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; NOSSE-NEXT: pushq %rbx
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; NOSSE-NEXT: movq %rsi, %rcx
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; NOSSE-NEXT: movq %rdi, %rbx
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; NOSSE-NEXT: movq _fsc128@{{.*}}(%rip), %rsi
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; NOSSE-NEXT: movq (%rsi), %rax
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; NOSSE-NEXT: movq 8(%rsi), %rdx
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; NOSSE-NEXT: .p2align 4, 0x90
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; NOSSE-NEXT: LBB0_1: ## %atomicrmw.start
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; NOSSE-NEXT: ## =>This Inner Loop Header: Depth=1
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; NOSSE-NEXT: lock cmpxchg16b (%rsi)
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; NOSSE-NEXT: jne LBB0_1
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; NOSSE-NEXT: ## %bb.2: ## %atomicrmw.end
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; NOSSE-NEXT: popq %rbx
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; NOSSE-NEXT: retq
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%t1 = atomicrmw xchg fp128* @fsc128, fp128 %x acquire
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ret void
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}
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