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bb08c0fdf8
As reported on PR39920, "slow horizontal ops" targets tend to internally expand to 2*shuffle+add/sub - so if we can reduce 2*shuffle+add/sub to a hadd/sub then we should do it - similar port usage but reduced instruction count. This works out in most cases, although the "PR22377" regression in vector-shuffle-combining.ll is annoying - going from 2*shuffle+add+shuffle to hadd+2*shuffle - I've opened PR41813 to cover this. Differential Revision: https://reviews.llvm.org/D61308 llvm-svn: 360360
134 lines
5.3 KiB
LLVM
134 lines
5.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-- -mattr=+avx2 | FileCheck %s --check-prefixes=X32,X32-SLOW
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; RUN: llc < %s -mtriple=i686-- -mattr=+avx2,fast-hops | FileCheck %s --check-prefixes=X32,X32-FAST
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefixes=X64,X64-SLOW
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2,fast-hops | FileCheck %s --check-prefixes=X64,X64-FAST
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define <16 x i16> @phaddw1(<16 x i16> %x, <16 x i16> %y) {
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; X32-LABEL: phaddw1:
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; X32: # %bb.0:
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; X32-NEXT: vphaddw %ymm1, %ymm0, %ymm0
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; X32-NEXT: retl
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;
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; X64-LABEL: phaddw1:
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; X64: # %bb.0:
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; X64-NEXT: vphaddw %ymm1, %ymm0, %ymm0
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; X64-NEXT: retq
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%a = shufflevector <16 x i16> %x, <16 x i16> %y, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22, i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>
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%b = shufflevector <16 x i16> %x, <16 x i16> %y, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 17, i32 19, i32 21, i32 23, i32 9, i32 11, i32 13, i32 15, i32 25, i32 27, i32 29, i32 31>
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%r = add <16 x i16> %a, %b
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ret <16 x i16> %r
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}
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define <16 x i16> @phaddw2(<16 x i16> %x, <16 x i16> %y) {
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; X32-LABEL: phaddw2:
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; X32: # %bb.0:
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; X32-NEXT: vphaddw %ymm1, %ymm0, %ymm0
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; X32-NEXT: retl
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;
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; X64-LABEL: phaddw2:
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; X64: # %bb.0:
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; X64-NEXT: vphaddw %ymm1, %ymm0, %ymm0
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; X64-NEXT: retq
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%a = shufflevector <16 x i16> %x, <16 x i16> %y, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 17, i32 19, i32 21, i32 23, i32 9, i32 11, i32 13, i32 15, i32 25, i32 27, i32 29, i32 31>
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%b = shufflevector <16 x i16> %y, <16 x i16> %x, <16 x i32> <i32 16, i32 18, i32 20, i32 22, i32 0, i32 2, i32 4, i32 6, i32 24, i32 26, i32 28, i32 30, i32 8, i32 10, i32 12, i32 14>
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%r = add <16 x i16> %a, %b
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ret <16 x i16> %r
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}
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define <8 x i32> @phaddd1(<8 x i32> %x, <8 x i32> %y) {
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; X32-LABEL: phaddd1:
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; X32: # %bb.0:
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; X32-NEXT: vphaddd %ymm1, %ymm0, %ymm0
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; X32-NEXT: retl
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;
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; X64-LABEL: phaddd1:
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; X64: # %bb.0:
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; X64-NEXT: vphaddd %ymm1, %ymm0, %ymm0
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; X64-NEXT: retq
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%a = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
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%b = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
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%r = add <8 x i32> %a, %b
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ret <8 x i32> %r
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}
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define <8 x i32> @phaddd2(<8 x i32> %x, <8 x i32> %y) {
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; X32-LABEL: phaddd2:
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; X32: # %bb.0:
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; X32-NEXT: vphaddd %ymm1, %ymm0, %ymm0
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; X32-NEXT: retl
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;
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; X64-LABEL: phaddd2:
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; X64: # %bb.0:
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; X64-NEXT: vphaddd %ymm1, %ymm0, %ymm0
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; X64-NEXT: retq
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%a = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 1, i32 2, i32 9, i32 10, i32 5, i32 6, i32 13, i32 14>
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%b = shufflevector <8 x i32> %y, <8 x i32> %x, <8 x i32> <i32 8, i32 11, i32 0, i32 3, i32 12, i32 15, i32 4, i32 7>
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%r = add <8 x i32> %a, %b
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ret <8 x i32> %r
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}
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define <8 x i32> @phaddd3(<8 x i32> %x) {
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; X32-LABEL: phaddd3:
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; X32: # %bb.0:
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; X32-NEXT: vphaddd %ymm0, %ymm0, %ymm0
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; X32-NEXT: retl
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;
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; X64-LABEL: phaddd3:
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; X64: # %bb.0:
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; X64-NEXT: vphaddd %ymm0, %ymm0, %ymm0
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; X64-NEXT: retq
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%a = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32 undef, i32 2, i32 8, i32 10, i32 4, i32 6, i32 undef, i32 14>
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%b = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32 1, i32 3, i32 9, i32 undef, i32 5, i32 7, i32 13, i32 15>
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%r = add <8 x i32> %a, %b
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ret <8 x i32> %r
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}
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define <16 x i16> @phsubw1(<16 x i16> %x, <16 x i16> %y) {
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; X32-LABEL: phsubw1:
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; X32: # %bb.0:
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; X32-NEXT: vphsubw %ymm1, %ymm0, %ymm0
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; X32-NEXT: retl
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;
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; X64-LABEL: phsubw1:
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; X64: # %bb.0:
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; X64-NEXT: vphsubw %ymm1, %ymm0, %ymm0
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; X64-NEXT: retq
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%a = shufflevector <16 x i16> %x, <16 x i16> %y, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22, i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>
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%b = shufflevector <16 x i16> %x, <16 x i16> %y, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 17, i32 19, i32 21, i32 23, i32 9, i32 11, i32 13, i32 15, i32 25, i32 27, i32 29, i32 31>
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%r = sub <16 x i16> %a, %b
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ret <16 x i16> %r
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}
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define <8 x i32> @phsubd1(<8 x i32> %x, <8 x i32> %y) {
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; X32-LABEL: phsubd1:
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; X32: # %bb.0:
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; X32-NEXT: vphsubd %ymm1, %ymm0, %ymm0
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; X32-NEXT: retl
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;
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; X64-LABEL: phsubd1:
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; X64: # %bb.0:
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; X64-NEXT: vphsubd %ymm1, %ymm0, %ymm0
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; X64-NEXT: retq
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%a = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
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%b = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
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%r = sub <8 x i32> %a, %b
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ret <8 x i32> %r
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}
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define <8 x i32> @phsubd2(<8 x i32> %x, <8 x i32> %y) {
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; X32-LABEL: phsubd2:
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; X32: # %bb.0:
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; X32-NEXT: vphsubd %ymm1, %ymm0, %ymm0
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; X32-NEXT: retl
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;
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; X64-LABEL: phsubd2:
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; X64: # %bb.0:
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; X64-NEXT: vphsubd %ymm1, %ymm0, %ymm0
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; X64-NEXT: retq
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%a = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 undef, i32 8, i32 undef, i32 4, i32 6, i32 12, i32 14>
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%b = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 1, i32 undef, i32 9, i32 11, i32 5, i32 7, i32 undef, i32 15>
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%r = sub <8 x i32> %a, %b
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ret <8 x i32> %r
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}
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