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38d740499a
As noted in PR43197, we can use test+add+cmov+sra to implement signed division by a power of 2. This is based off the similar version in AArch64, but I've adjusted it to use target independent nodes where AArch64 uses target specific CMP and CSEL nodes. I've also blocked INT_MIN as the transform isn't valid for that. I've limited this to i32 and i64 on 64-bit targets for now and only when CMOV is supported. i8 and i16 need further investigation to be sure they get promoted to i32 well. I adjusted a few tests to enable cmov to demonstrate the new codegen. I also changed twoaddr-coalesce-3.ll to 32-bit mode without cmov to avoid perturbing the scenario that is being set up there. Differential Revision: https://reviews.llvm.org/D67087 llvm-svn: 371104
80 lines
2.1 KiB
LLVM
80 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+cmov | FileCheck %s
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define i32 @test1(i32 %X) {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl $-2139062143, %edx # imm = 0x80808081
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: imull %edx
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; CHECK-NEXT: addl %ecx, %edx
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: shrl $31, %eax
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; CHECK-NEXT: sarl $7, %edx
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; CHECK-NEXT: addl %eax, %edx
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: shll $8, %eax
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; CHECK-NEXT: subl %eax, %edx
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; CHECK-NEXT: addl %edx, %ecx
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: retl
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%tmp1 = srem i32 %X, 255
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ret i32 %tmp1
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}
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define i32 @test2(i32 %X) {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: leal 255(%eax), %ecx
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; CHECK-NEXT: testl %eax, %eax
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; CHECK-NEXT: cmovnsl %eax, %ecx
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; CHECK-NEXT: andl $-256, %ecx
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; CHECK-NEXT: subl %ecx, %eax
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; CHECK-NEXT: retl
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%tmp1 = srem i32 %X, 256
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ret i32 %tmp1
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}
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define i32 @test3(i32 %X) {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl $-2139062143, %edx # imm = 0x80808081
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: mull %edx
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; CHECK-NEXT: shrl $7, %edx
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: shll $8, %eax
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; CHECK-NEXT: subl %eax, %edx
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; CHECK-NEXT: addl %edx, %ecx
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: retl
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%tmp1 = urem i32 %X, 255
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ret i32 %tmp1
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}
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define i32 @test4(i32 %X) {
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; CHECK-LABEL: test4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: retl
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%tmp1 = urem i32 %X, 256
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ret i32 %tmp1
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}
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define i32 @test5(i32 %X) nounwind readnone {
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; CHECK-LABEL: test5:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl $41, %eax
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: idivl {{[0-9]+}}(%esp)
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: retl
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entry:
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%0 = srem i32 41, %X
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ret i32 %0
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}
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