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5d9cb0f9f9
If whole quad mode isn't enabled for these, the level of detail is calculated incorrectly for pixels along diagonal triangle edges, causing artifacts. v2: Use a TSFlag instead of lots of switch cases v3: Add test coverage Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88642 Reviewed-by: Tom Stellard <tom@stellard.net> llvm-svn: 228372
641 lines
14 KiB
TableGen
641 lines
14 KiB
TableGen
//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// SI Instruction format definitions.
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//
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//===----------------------------------------------------------------------===//
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class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
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AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
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field bits<1> VM_CNT = 0;
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field bits<1> EXP_CNT = 0;
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field bits<1> LGKM_CNT = 0;
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field bits<1> SALU = 0;
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field bits<1> VALU = 0;
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field bits<1> SOP1 = 0;
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field bits<1> SOP2 = 0;
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field bits<1> SOPC = 0;
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field bits<1> SOPK = 0;
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field bits<1> SOPP = 0;
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field bits<1> VOP1 = 0;
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field bits<1> VOP2 = 0;
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field bits<1> VOP3 = 0;
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field bits<1> VOPC = 0;
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field bits<1> MUBUF = 0;
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field bits<1> MTBUF = 0;
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field bits<1> SMRD = 0;
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field bits<1> DS = 0;
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field bits<1> MIMG = 0;
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field bits<1> FLAT = 0;
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field bits<1> WQM = 0;
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// These need to be kept in sync with the enum in SIInstrFlags.
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let TSFlags{0} = VM_CNT;
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let TSFlags{1} = EXP_CNT;
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let TSFlags{2} = LGKM_CNT;
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let TSFlags{3} = SALU;
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let TSFlags{4} = VALU;
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let TSFlags{5} = SOP1;
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let TSFlags{6} = SOP2;
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let TSFlags{7} = SOPC;
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let TSFlags{8} = SOPK;
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let TSFlags{9} = SOPP;
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let TSFlags{10} = VOP1;
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let TSFlags{11} = VOP2;
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let TSFlags{12} = VOP3;
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let TSFlags{13} = VOPC;
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let TSFlags{14} = MUBUF;
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let TSFlags{15} = MTBUF;
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let TSFlags{16} = SMRD;
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let TSFlags{17} = DS;
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let TSFlags{18} = MIMG;
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let TSFlags{19} = FLAT;
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let TSFlags{20} = WQM;
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// Most instructions require adjustments after selection to satisfy
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// operand requirements.
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let hasPostISelHook = 1;
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let SchedRW = [Write32Bit];
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}
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class Enc32 {
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field bits<32> Inst;
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int Size = 4;
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}
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class Enc64 {
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field bits<64> Inst;
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int Size = 8;
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}
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let Uses = [EXEC] in {
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class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI <outs, ins, asm, pattern> {
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let UseNamedOperandTable = 1;
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let VALU = 1;
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}
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class VOPCCommon <dag ins, string asm, list<dag> pattern> :
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VOPAnyCommon <(outs VCCReg:$dst), ins, asm, pattern> {
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let DisableEncoding = "$dst";
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let VOPC = 1;
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let Size = 4;
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}
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class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> :
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VOPAnyCommon <outs, ins, asm, pattern> {
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let VOP1 = 1;
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let Size = 4;
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}
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class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> :
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VOPAnyCommon <outs, ins, asm, pattern> {
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let VOP2 = 1;
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let Size = 4;
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}
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class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
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VOPAnyCommon <outs, ins, asm, pattern> {
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// Using complex patterns gives VOP3 patterns a very high complexity rating,
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// but standalone patterns are almost always prefered, so we need to adjust the
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// priority lower. The goal is to use a high number to reduce complexity to
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// zero (or less than zero).
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let AddedComplexity = -1000;
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let VOP3 = 1;
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int Size = 8;
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}
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} // End Uses = [EXEC]
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//===----------------------------------------------------------------------===//
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// Scalar operations
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//===----------------------------------------------------------------------===//
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class SOP1e <bits<8> op> : Enc32 {
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bits<7> SDST;
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bits<8> SSRC0;
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let Inst{7-0} = SSRC0;
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let Inst{15-8} = op;
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let Inst{22-16} = SDST;
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let Inst{31-23} = 0x17d; //encoding;
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}
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class SOP2e <bits<7> op> : Enc32 {
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bits<7> SDST;
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bits<8> SSRC0;
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bits<8> SSRC1;
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let Inst{7-0} = SSRC0;
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let Inst{15-8} = SSRC1;
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let Inst{22-16} = SDST;
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let Inst{29-23} = op;
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let Inst{31-30} = 0x2; // encoding
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}
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class SOPCe <bits<7> op> : Enc32 {
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bits<8> SSRC0;
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bits<8> SSRC1;
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let Inst{7-0} = SSRC0;
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let Inst{15-8} = SSRC1;
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let Inst{22-16} = op;
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let Inst{31-23} = 0x17e;
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}
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class SOPKe <bits<5> op> : Enc32 {
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bits <7> SDST;
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bits <16> SIMM16;
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let Inst{15-0} = SIMM16;
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let Inst{22-16} = SDST;
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let Inst{27-23} = op;
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let Inst{31-28} = 0xb; //encoding
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}
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class SOPPe <bits<7> op> : Enc32 {
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bits <16> simm16;
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let Inst{15-0} = simm16;
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let Inst{22-16} = op;
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let Inst{31-23} = 0x17f; // encoding
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}
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class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
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bits<7> SDST;
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bits<7> SBASE;
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bits<8> OFFSET;
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let Inst{7-0} = OFFSET;
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let Inst{8} = imm;
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let Inst{14-9} = SBASE{6-1};
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let Inst{21-15} = SDST;
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let Inst{26-22} = op;
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let Inst{31-27} = 0x18; //encoding
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}
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let SchedRW = [WriteSALU] in {
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class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI<outs, ins, asm, pattern> {
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let SALU = 1;
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let SOP1 = 1;
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}
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class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI <outs, ins, asm, pattern> {
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let SALU = 1;
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let SOP2 = 1;
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let UseNamedOperandTable = 1;
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}
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class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI<outs, ins, asm, pattern>, SOPCe <op> {
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let DisableEncoding = "$dst";
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let SALU = 1;
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let SOPC = 1;
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let UseNamedOperandTable = 1;
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}
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class SOPK <dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI <outs, ins , asm, pattern> {
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let SALU = 1;
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let SOPK = 1;
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let UseNamedOperandTable = 1;
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}
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class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
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InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let isCodeGenOnly = 0;
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let SALU = 1;
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let SOPP = 1;
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let UseNamedOperandTable = 1;
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}
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} // let SchedRW = [WriteSALU]
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class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI<outs, ins, asm, pattern> {
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let LGKM_CNT = 1;
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let SMRD = 1;
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let mayStore = 0;
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let mayLoad = 1;
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let hasSideEffects = 0;
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let UseNamedOperandTable = 1;
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let SchedRW = [WriteSMEM];
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}
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//===----------------------------------------------------------------------===//
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// Vector ALU operations
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//===----------------------------------------------------------------------===//
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class VOP1e <bits<8> op> : Enc32 {
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bits<8> VDST;
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bits<9> SRC0;
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let Inst{8-0} = SRC0;
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let Inst{16-9} = op;
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let Inst{24-17} = VDST;
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let Inst{31-25} = 0x3f; //encoding
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}
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class VOP2e <bits<6> op> : Enc32 {
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bits<8> VDST;
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bits<9> SRC0;
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bits<8> VSRC1;
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let Inst{8-0} = SRC0;
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let Inst{16-9} = VSRC1;
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let Inst{24-17} = VDST;
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let Inst{30-25} = op;
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let Inst{31} = 0x0; //encoding
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}
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class VOP3e <bits<9> op> : Enc64 {
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bits<8> dst;
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bits<2> src0_modifiers;
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bits<9> src0;
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bits<2> src1_modifiers;
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bits<9> src1;
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bits<2> src2_modifiers;
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bits<9> src2;
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bits<1> clamp;
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bits<2> omod;
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let Inst{7-0} = dst;
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let Inst{8} = src0_modifiers{1};
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let Inst{9} = src1_modifiers{1};
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let Inst{10} = src2_modifiers{1};
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let Inst{11} = clamp;
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let Inst{25-17} = op;
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let Inst{31-26} = 0x34; //encoding
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let Inst{40-32} = src0;
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let Inst{49-41} = src1;
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let Inst{58-50} = src2;
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let Inst{60-59} = omod;
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let Inst{61} = src0_modifiers{0};
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let Inst{62} = src1_modifiers{0};
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let Inst{63} = src2_modifiers{0};
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}
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class VOP3be <bits<9> op> : Enc64 {
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bits<8> dst;
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bits<2> src0_modifiers;
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bits<9> src0;
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bits<2> src1_modifiers;
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bits<9> src1;
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bits<2> src2_modifiers;
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bits<9> src2;
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bits<7> sdst;
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bits<2> omod;
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let Inst{7-0} = dst;
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let Inst{14-8} = sdst;
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let Inst{25-17} = op;
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let Inst{31-26} = 0x34; //encoding
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let Inst{40-32} = src0;
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let Inst{49-41} = src1;
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let Inst{58-50} = src2;
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let Inst{60-59} = omod;
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let Inst{61} = src0_modifiers{0};
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let Inst{62} = src1_modifiers{0};
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let Inst{63} = src2_modifiers{0};
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}
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class VOPCe <bits<8> op> : Enc32 {
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bits<9> SRC0;
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bits<8> VSRC1;
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let Inst{8-0} = SRC0;
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let Inst{16-9} = VSRC1;
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let Inst{24-17} = op;
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let Inst{31-25} = 0x3e;
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}
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class VINTRPe <bits<2> op> : Enc32 {
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bits<8> VDST;
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bits<8> VSRC;
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bits<2> ATTRCHAN;
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bits<6> ATTR;
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let Inst{7-0} = VSRC;
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let Inst{9-8} = ATTRCHAN;
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let Inst{15-10} = ATTR;
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let Inst{17-16} = op;
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let Inst{25-18} = VDST;
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let Inst{31-26} = 0x32; // encoding
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}
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class DSe <bits<8> op> : Enc64 {
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bits<8> vdst;
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bits<1> gds;
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bits<8> addr;
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bits<8> data0;
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bits<8> data1;
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bits<8> offset0;
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bits<8> offset1;
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let Inst{7-0} = offset0;
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let Inst{15-8} = offset1;
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let Inst{17} = gds;
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let Inst{25-18} = op;
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let Inst{31-26} = 0x36; //encoding
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let Inst{39-32} = addr;
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let Inst{47-40} = data0;
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let Inst{55-48} = data1;
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let Inst{63-56} = vdst;
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}
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class MUBUFe <bits<7> op> : Enc64 {
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bits<12> offset;
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bits<1> offen;
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bits<1> idxen;
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bits<1> glc;
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bits<1> addr64;
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bits<1> lds;
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bits<8> vaddr;
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bits<8> vdata;
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bits<7> srsrc;
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bits<1> slc;
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bits<1> tfe;
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bits<8> soffset;
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let Inst{11-0} = offset;
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let Inst{12} = offen;
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let Inst{13} = idxen;
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let Inst{14} = glc;
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let Inst{15} = addr64;
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let Inst{16} = lds;
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let Inst{24-18} = op;
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let Inst{31-26} = 0x38; //encoding
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let Inst{39-32} = vaddr;
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let Inst{47-40} = vdata;
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let Inst{52-48} = srsrc{6-2};
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let Inst{54} = slc;
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let Inst{55} = tfe;
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let Inst{63-56} = soffset;
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}
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class MTBUFe <bits<3> op> : Enc64 {
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bits<8> VDATA;
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bits<12> OFFSET;
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bits<1> OFFEN;
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bits<1> IDXEN;
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bits<1> GLC;
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bits<1> ADDR64;
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bits<4> DFMT;
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bits<3> NFMT;
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bits<8> VADDR;
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bits<7> SRSRC;
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bits<1> SLC;
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bits<1> TFE;
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bits<8> SOFFSET;
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let Inst{11-0} = OFFSET;
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let Inst{12} = OFFEN;
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let Inst{13} = IDXEN;
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let Inst{14} = GLC;
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let Inst{15} = ADDR64;
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let Inst{18-16} = op;
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let Inst{22-19} = DFMT;
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let Inst{25-23} = NFMT;
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let Inst{31-26} = 0x3a; //encoding
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let Inst{39-32} = VADDR;
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let Inst{47-40} = VDATA;
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let Inst{52-48} = SRSRC{6-2};
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let Inst{54} = SLC;
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let Inst{55} = TFE;
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let Inst{63-56} = SOFFSET;
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}
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class MIMGe <bits<7> op> : Enc64 {
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bits<8> VDATA;
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bits<4> DMASK;
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bits<1> UNORM;
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bits<1> GLC;
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bits<1> DA;
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bits<1> R128;
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bits<1> TFE;
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bits<1> LWE;
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bits<1> SLC;
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bits<8> VADDR;
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bits<7> SRSRC;
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bits<7> SSAMP;
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let Inst{11-8} = DMASK;
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let Inst{12} = UNORM;
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let Inst{13} = GLC;
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let Inst{14} = DA;
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let Inst{15} = R128;
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let Inst{16} = TFE;
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let Inst{17} = LWE;
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let Inst{24-18} = op;
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let Inst{25} = SLC;
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let Inst{31-26} = 0x3c;
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let Inst{39-32} = VADDR;
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let Inst{47-40} = VDATA;
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let Inst{52-48} = SRSRC{6-2};
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let Inst{57-53} = SSAMP{6-2};
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}
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class FLATe<bits<7> op> : Enc64 {
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bits<8> addr;
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bits<8> data;
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bits<8> vdst;
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bits<1> slc;
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bits<1> glc;
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bits<1> tfe;
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// 15-0 is reserved.
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let Inst{16} = glc;
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let Inst{17} = slc;
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let Inst{24-18} = op;
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let Inst{31-26} = 0x37; // Encoding.
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let Inst{39-32} = addr;
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let Inst{47-40} = data;
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// 54-48 is reserved.
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let Inst{55} = tfe;
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let Inst{63-56} = vdst;
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|
}
|
|
|
|
class EXPe : Enc64 {
|
|
bits<4> EN;
|
|
bits<6> TGT;
|
|
bits<1> COMPR;
|
|
bits<1> DONE;
|
|
bits<1> VM;
|
|
bits<8> VSRC0;
|
|
bits<8> VSRC1;
|
|
bits<8> VSRC2;
|
|
bits<8> VSRC3;
|
|
|
|
let Inst{3-0} = EN;
|
|
let Inst{9-4} = TGT;
|
|
let Inst{10} = COMPR;
|
|
let Inst{11} = DONE;
|
|
let Inst{12} = VM;
|
|
let Inst{31-26} = 0x3e;
|
|
let Inst{39-32} = VSRC0;
|
|
let Inst{47-40} = VSRC1;
|
|
let Inst{55-48} = VSRC2;
|
|
let Inst{63-56} = VSRC3;
|
|
}
|
|
|
|
let Uses = [EXEC] in {
|
|
|
|
class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
|
VOP1Common <outs, ins, asm, pattern>,
|
|
VOP1e<op>;
|
|
|
|
class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
|
VOP2Common <outs, ins, asm, pattern>, VOP2e<op>;
|
|
|
|
class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
|
VOP3Common <outs, ins, asm, pattern>, VOP3be<op>;
|
|
|
|
class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
|
|
VOPCCommon <ins, asm, pattern>, VOPCe <op>;
|
|
|
|
class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
|
|
InstSI <outs, ins, asm, pattern> {
|
|
let mayLoad = 1;
|
|
let mayStore = 0;
|
|
let hasSideEffects = 0;
|
|
}
|
|
|
|
} // End Uses = [EXEC]
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Vector I/O operations
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let Uses = [EXEC] in {
|
|
|
|
class DS <dag outs, dag ins, string asm, list<dag> pattern> :
|
|
InstSI <outs, ins, asm, pattern> {
|
|
|
|
let LGKM_CNT = 1;
|
|
let DS = 1;
|
|
let UseNamedOperandTable = 1;
|
|
let DisableEncoding = "$m0";
|
|
let SchedRW = [WriteLDS];
|
|
}
|
|
|
|
class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> :
|
|
InstSI<outs, ins, asm, pattern> {
|
|
|
|
let VM_CNT = 1;
|
|
let EXP_CNT = 1;
|
|
let MUBUF = 1;
|
|
|
|
let hasSideEffects = 0;
|
|
let UseNamedOperandTable = 1;
|
|
let SchedRW = [WriteVMEM];
|
|
}
|
|
|
|
class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> :
|
|
InstSI<outs, ins, asm, pattern> {
|
|
|
|
let VM_CNT = 1;
|
|
let EXP_CNT = 1;
|
|
let MTBUF = 1;
|
|
|
|
let hasSideEffects = 0;
|
|
let UseNamedOperandTable = 1;
|
|
let SchedRW = [WriteVMEM];
|
|
}
|
|
|
|
class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
|
InstSI<outs, ins, asm, pattern>, FLATe <op> {
|
|
let FLAT = 1;
|
|
// Internally, FLAT instruction are executed as both an LDS and a
|
|
// Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
|
|
// and are not considered done until both have been decremented.
|
|
let VM_CNT = 1;
|
|
let LGKM_CNT = 1;
|
|
|
|
let Uses = [EXEC, FLAT_SCR]; // M0
|
|
|
|
let UseNamedOperandTable = 1;
|
|
let hasSideEffects = 0;
|
|
}
|
|
|
|
class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
|
InstSI <outs, ins, asm, pattern>, MIMGe <op> {
|
|
|
|
let VM_CNT = 1;
|
|
let EXP_CNT = 1;
|
|
let MIMG = 1;
|
|
|
|
let hasSideEffects = 0; // XXX ????
|
|
}
|
|
|
|
|
|
} // End Uses = [EXEC]
|