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1d61f2cb75
Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
215 lines
6.2 KiB
C++
215 lines
6.2 KiB
C++
//==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file provides WebAssembly-specific target descriptions.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
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#define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
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#include "llvm/BinaryFormat/Wasm.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Support/DataTypes.h"
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#include <memory>
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namespace llvm {
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class MCAsmBackend;
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class MCCodeEmitter;
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class MCContext;
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class MCInstrInfo;
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class MCObjectTargetWriter;
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class MCSubtargetInfo;
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class MVT;
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class Target;
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class Triple;
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class raw_pwrite_stream;
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Target &getTheWebAssemblyTarget32();
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Target &getTheWebAssemblyTarget64();
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MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII);
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MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT);
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std::unique_ptr<MCObjectTargetWriter>
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createWebAssemblyELFObjectWriter(bool Is64Bit, uint8_t OSABI);
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std::unique_ptr<MCObjectTargetWriter>
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createWebAssemblyWasmObjectWriter(bool Is64Bit);
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namespace WebAssembly {
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enum OperandType {
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/// Basic block label in a branch construct.
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OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET,
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/// Local index.
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OPERAND_LOCAL,
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/// Global index.
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OPERAND_GLOBAL,
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/// 32-bit integer immediates.
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OPERAND_I32IMM,
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/// 64-bit integer immediates.
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OPERAND_I64IMM,
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/// 32-bit floating-point immediates.
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OPERAND_F32IMM,
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/// 64-bit floating-point immediates.
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OPERAND_F64IMM,
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/// 32-bit unsigned function indices.
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OPERAND_FUNCTION32,
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/// 32-bit unsigned memory offsets.
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OPERAND_OFFSET32,
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/// p2align immediate for load and store address alignment.
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OPERAND_P2ALIGN,
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/// signature immediate for block/loop.
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OPERAND_SIGNATURE,
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/// type signature immediate for call_indirect.
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OPERAND_TYPEINDEX,
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};
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} // end namespace WebAssembly
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namespace WebAssemblyII {
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enum {
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// For variadic instructions, this flag indicates whether an operand
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// in the variable_ops range is an immediate value.
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VariableOpIsImmediate = (1 << 0),
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// For immediate values in the variable_ops range, this flag indicates
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// whether the value represents a control-flow label.
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VariableOpImmediateIsLabel = (1 << 1)
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};
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} // end namespace WebAssemblyII
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} // end namespace llvm
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// Defines symbolic names for WebAssembly registers. This defines a mapping from
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// register name to register number.
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//
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#define GET_REGINFO_ENUM
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#include "WebAssemblyGenRegisterInfo.inc"
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// Defines symbolic names for the WebAssembly instructions.
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//
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#define GET_INSTRINFO_ENUM
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#include "WebAssemblyGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_ENUM
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#include "WebAssemblyGenSubtargetInfo.inc"
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namespace llvm {
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namespace WebAssembly {
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/// Return the default p2align value for a load or store with the given opcode.
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inline unsigned GetDefaultP2Align(unsigned Opcode) {
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switch (Opcode) {
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case WebAssembly::LOAD8_S_I32:
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case WebAssembly::LOAD8_S_I32_S:
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case WebAssembly::LOAD8_U_I32:
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case WebAssembly::LOAD8_U_I32_S:
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case WebAssembly::LOAD8_S_I64:
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case WebAssembly::LOAD8_S_I64_S:
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case WebAssembly::LOAD8_U_I64:
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case WebAssembly::LOAD8_U_I64_S:
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case WebAssembly::ATOMIC_LOAD8_U_I32:
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case WebAssembly::ATOMIC_LOAD8_U_I32_S:
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case WebAssembly::ATOMIC_LOAD8_U_I64:
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case WebAssembly::ATOMIC_LOAD8_U_I64_S:
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case WebAssembly::STORE8_I32:
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case WebAssembly::STORE8_I32_S:
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case WebAssembly::STORE8_I64:
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case WebAssembly::STORE8_I64_S:
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return 0;
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case WebAssembly::LOAD16_S_I32:
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case WebAssembly::LOAD16_S_I32_S:
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case WebAssembly::LOAD16_U_I32:
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case WebAssembly::LOAD16_U_I32_S:
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case WebAssembly::LOAD16_S_I64:
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case WebAssembly::LOAD16_S_I64_S:
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case WebAssembly::LOAD16_U_I64:
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case WebAssembly::LOAD16_U_I64_S:
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case WebAssembly::ATOMIC_LOAD16_U_I32:
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case WebAssembly::ATOMIC_LOAD16_U_I32_S:
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case WebAssembly::ATOMIC_LOAD16_U_I64:
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case WebAssembly::ATOMIC_LOAD16_U_I64_S:
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case WebAssembly::STORE16_I32:
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case WebAssembly::STORE16_I32_S:
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case WebAssembly::STORE16_I64:
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case WebAssembly::STORE16_I64_S:
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return 1;
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case WebAssembly::LOAD_I32:
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case WebAssembly::LOAD_I32_S:
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case WebAssembly::LOAD_F32:
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case WebAssembly::LOAD_F32_S:
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case WebAssembly::STORE_I32:
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case WebAssembly::STORE_I32_S:
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case WebAssembly::STORE_F32:
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case WebAssembly::STORE_F32_S:
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case WebAssembly::LOAD32_S_I64:
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case WebAssembly::LOAD32_S_I64_S:
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case WebAssembly::LOAD32_U_I64:
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case WebAssembly::LOAD32_U_I64_S:
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case WebAssembly::STORE32_I64:
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case WebAssembly::STORE32_I64_S:
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case WebAssembly::ATOMIC_LOAD_I32:
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case WebAssembly::ATOMIC_LOAD_I32_S:
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case WebAssembly::ATOMIC_LOAD32_U_I64:
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case WebAssembly::ATOMIC_LOAD32_U_I64_S:
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return 2;
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case WebAssembly::LOAD_I64:
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case WebAssembly::LOAD_I64_S:
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case WebAssembly::LOAD_F64:
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case WebAssembly::LOAD_F64_S:
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case WebAssembly::STORE_I64:
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case WebAssembly::STORE_I64_S:
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case WebAssembly::STORE_F64:
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case WebAssembly::STORE_F64_S:
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case WebAssembly::ATOMIC_LOAD_I64:
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case WebAssembly::ATOMIC_LOAD_I64_S:
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return 3;
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default:
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llvm_unreachable("Only loads and stores have p2align values");
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}
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}
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/// The operand number of the load or store address in load/store instructions.
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static const unsigned LoadAddressOperandNo = 3;
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static const unsigned StoreAddressOperandNo = 2;
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/// The operand number of the load or store p2align in load/store instructions.
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static const unsigned LoadP2AlignOperandNo = 1;
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static const unsigned StoreP2AlignOperandNo = 0;
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/// This is used to indicate block signatures.
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enum class ExprType : unsigned {
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Void = 0x40,
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I32 = 0x7F,
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I64 = 0x7E,
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F32 = 0x7D,
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F64 = 0x7C,
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I8x16 = 0x7B,
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I16x8 = 0x7A,
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I32x4 = 0x79,
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F32x4 = 0x78,
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B8x16 = 0x77,
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B16x8 = 0x76,
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B32x4 = 0x75,
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ExceptRef = 0x68
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};
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/// Instruction opcodes emitted via means other than CodeGen.
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static const unsigned Nop = 0x01;
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static const unsigned End = 0x0b;
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wasm::ValType toValType(const MVT &Ty);
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} // end namespace WebAssembly
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} // end namespace llvm
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#endif
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