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d3615c630c
Summary: This lowers exception catching-related instructions: 1. Lowers `wasm.catch` intrinsic to `catch` instruction 2. Removes `catchpad` and `cleanuppad` instructions; they are not necessary after isel phase. (`MachineBasicBlock::isEHFuncletEntry()` or `MachineBasicBlock::isEHPad()` can be used instead.) 3. Lowers `catchret` and `cleanupret` instructions to pseudo `catchret` and `cleanupret` instructions in isel, which will be replaced with other instructions in `WebAssemblyExceptionPrepare` pass. 4. Adds 'WebAssemblyExceptionPrepare` pass, which is for running various transformation for EH. Currently this pass only replaces `catchret` and `cleanupret` instructions into appropriate wasm instructions to make this patch successfully run until the end. Currently this does not handle lowering of intrinsics related to LSDA info generation (`wasm.landingpad.index` and `wasm.lsda`), because they cannot be tested without implementing `EHStreamer`'s wasm-specific handlers. They are marked as TODO, which is needed to make isel pass. Also this does not generate `try` and `end_try` markers yet, which will be handled in later patches. This patch is based on the first wasm EH proposal. (https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md) Reviewers: dschuff, majnemer Subscribers: jfb, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D44090 llvm-svn: 333705
104 lines
4.3 KiB
C++
104 lines
4.3 KiB
C++
//- WebAssemblyISelLowering.h - WebAssembly DAG Lowering Interface -*- C++ -*-//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file defines the interfaces that WebAssembly uses to lower LLVM
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/// code into a selection DAG.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYISELLOWERING_H
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#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYISELLOWERING_H
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#include "llvm/CodeGen/TargetLowering.h"
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namespace llvm {
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namespace WebAssemblyISD {
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enum NodeType : unsigned {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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#define HANDLE_NODETYPE(NODE) NODE,
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#include "WebAssemblyISD.def"
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#undef HANDLE_NODETYPE
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};
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} // end namespace WebAssemblyISD
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class WebAssemblySubtarget;
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class WebAssemblyTargetMachine;
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class WebAssemblyTargetLowering final : public TargetLowering {
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public:
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WebAssemblyTargetLowering(const TargetMachine &TM,
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const WebAssemblySubtarget &STI);
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private:
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/// Keep a pointer to the WebAssemblySubtarget around so that we can make the
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/// right decision when generating code for different targets.
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const WebAssemblySubtarget *Subtarget;
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FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
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const TargetLibraryInfo *LibInfo) const override;
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bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *MBB) const override;
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const char *getTargetNodeName(unsigned Opcode) const override;
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std::pair<unsigned, const TargetRegisterClass *> getRegForInlineAsmConstraint(
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const TargetRegisterInfo *TRI, StringRef Constraint,
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MVT VT) const override;
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bool isCheapToSpeculateCttz() const override;
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bool isCheapToSpeculateCtlz() const override;
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bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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unsigned AS,
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Instruction *I = nullptr) const override;
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bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace, unsigned Align,
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bool *Fast) const override;
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bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
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SDValue LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
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SelectionDAG &DAG) const override;
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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// Custom lowering hooks.
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCopyToReg(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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};
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namespace WebAssembly {
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FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
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const TargetLibraryInfo *libInfo);
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} // end namespace WebAssembly
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} // end namespace llvm
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#endif
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