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llvm-mirror/test/MC
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Georgii Rymar c7112b7126 [llvm-readobj] - For SHT_REL relocations, don't display an addend. 
This is https://bugs.llvm.org/show_bug.cgi?id=44257.

In LLVM style we always print `0` as addend when dumping
SHT_REL relocations. It is confusing, this patch stops
printing it as the first comment on the bug page suggests.

Differential revision: https://reviews.llvm.org/D93033
2020-12-14 12:03:00 +03:00
..
AArch64 [Triple][MachO] Define "arm64e", an AArch64 subarch for Pointer Auth. 2020-12-03 07:53:59 -08:00
AMDGPU [llvm-readobj] - For SHT_REL relocations, don't display an addend. 2020-12-14 12:03:00 +03:00
ARM [llvm-readobj] - For SHT_REL relocations, don't display an addend. 2020-12-14 12:03:00 +03:00
AsmParser [MC] Fix ICE with non-newline terminated input 2020-12-09 23:39:32 +00:00
AVR [AVRInstPrinter] printOperand: support llvm-objdump --print-imm-hex 2020-07-12 08:14:52 -07:00
BPF
COFF [CodeView] Fix inline sites that are missing code offsets. 2020-12-07 13:01:53 -08:00
Disassembler [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump 2020-12-04 10:34:12 -08:00
ELF [llvm-readobj] - For SHT_REL relocations, don't display an addend. 2020-12-14 12:03:00 +03:00
Hexagon [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
Lanai
MachO [Triple][MachO] Define "arm64e", an AArch64 subarch for Pointer Auth. 2020-12-03 07:53:59 -08:00
Mips [llvm-readobj] - For SHT_REL relocations, don't display an addend. 2020-12-14 12:03:00 +03:00
MSP430 [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
PowerPC [PowerPC] Correct the bit-width definition for some imm operand in td. 2020-12-08 03:20:12 +00:00
RISCV [RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions 2020-12-10 19:25:51 +00:00
Sparc [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
SystemZ [SystemZ] Adding extra extended mnemonics for SystemZ target 2020-12-02 08:25:31 -05:00
VE [VE] Add missing BCR format 2020-10-29 23:30:49 +09:00
WebAssembly [WebAssembly] Support COMDAT sections in assembly syntax 2020-12-10 16:43:59 -08:00
X86 [llvm-readobj] - For SHT_REL relocations, don't display an addend. 2020-12-14 12:03:00 +03:00