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59 lines
2.1 KiB
C++
59 lines
2.1 KiB
C++
//===- IA64InstrInfo.cpp - IA64 Instruction Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the IA64 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "IA64InstrInfo.h"
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#include "IA64.h"
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#include "IA64InstrBuilder.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "IA64GenInstrInfo.inc"
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using namespace llvm;
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IA64InstrInfo::IA64InstrInfo()
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: TargetInstrInfo(IA64Insts, sizeof(IA64Insts)/sizeof(IA64Insts[0])),
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RI(*this) {
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}
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bool IA64InstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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MachineOpCode oc = MI.getOpcode();
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if (oc == IA64::MOV || oc == IA64::FMOV) {
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// TODO: this doesn't detect predicate moves
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assert(MI.getNumOperands() >= 2 &&
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/* MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() && */
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"invalid register-register move instruction");
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if( MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() ) {
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// if both operands of the MOV/FMOV are registers, then
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// yes, this is a move instruction
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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}
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return false; // we don't consider e.g. %regN = MOV <FrameIndex #x> a
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// move instruction
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}
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unsigned
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IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const std::vector<MachineOperand> &Cond)const {
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// Can only insert uncond branches so far.
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assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
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BuildMI(&MBB, get(IA64::BRL_NOTCALL)).addMBB(TBB);
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return 1;
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}
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