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86fa0255b2
The way the named arguments for various system instructions are handled at the
moment has a few problems:
- Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp
- That weird Mapping class that I have no idea what I was on when I thought
it was a good idea.
- Searches are performed linearly through the entire list.
- We print absolutely all registers in upper-case, even though some are
canonically mixed case (SPSel for example).
- The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated
to comments in our implementation, with a slightly opaque hex value
indicating the canonical encoding LLVM will use.
This adds a new TableGen backend to produce efficiently searchable tables, and
switches AArch64 over to using that infrastructure.
llvm-svn: 274576
25 lines
892 B
ArmAsm
25 lines
892 B
ArmAsm
// RUN: not llvm-mc -triple arm64 -show-encoding < %s 2>%t | FileCheck %s
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// RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
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msr SPSel, #0
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msr SPSel, x0
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msr DAIFSet, #0
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msr ESR_EL1, x0
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mrs x0, SPSel
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mrs x0, ESR_EL1
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// CHECK: msr SPSel, #0 // encoding: [0xbf,0x40,0x00,0xd5]
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// CHECK: msr SPSel, x0 // encoding: [0x00,0x42,0x18,0xd5]
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// CHECK: msr DAIFSet, #0 // encoding: [0xdf,0x40,0x03,0xd5]
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// CHECK: msr ESR_EL1, x0 // encoding: [0x00,0x52,0x18,0xd5]
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// CHECK: mrs x0, SPSel // encoding: [0x00,0x42,0x38,0xd5]
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// CHECK: mrs x0, ESR_EL1 // encoding: [0x00,0x52,0x38,0xd5]
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msr DAIFSet, x0
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msr ESR_EL1, #0
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mrs x0, DAIFSet
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// CHECK-ERRORS: error: immediate must be an integer in range [0, 15]
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// CHECK-ERRORS: error: invalid operand for instruction
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// CHECK-ERRORS: error: expected readable system register
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