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f58953b936
Move expected-fail cases from directive-cpu.s to directive-cpu-err.s. This allows us to remove the 'not' from the llvm-mc invocation in directive-cpu.s so that this test will fail in unexpected error cases. It also means that we are not relying on all stderr coming before any stdout, which seems fragile. Also make use of CHECK-NEXT to ensure that multiline error messages really are occuring together. And add a test to verify that .cpu with an arch version as extension is rejected. Differential Revision: https://reviews.llvm.org/D47873 llvm-svn: 335586
58 lines
1.2 KiB
ArmAsm
58 lines
1.2 KiB
ArmAsm
// RUN: not llvm-mc -triple aarch64-unknown-none-eabi -filetype asm -o - %s 2>&1 | FileCheck %s
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.arch axp64
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# CHECK: error: unknown arch name
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# CHECK-NEXT: .arch axp64
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# CHECK-NEXT: ^
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.arch armv8
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aese v0.8h, v1.8h
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: aese v0.8h, v1.8h
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# CHECK-NEXT: ^
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// We silently ignore invalid features.
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.arch armv8+foo
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aese v0.8h, v1.8h
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: aese v0.8h, v1.8h
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# CHECK-NEXT: ^
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.arch armv8+crypto
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.arch armv8
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aese v0.8h, v1.8h
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: aese v0.8h, v1.8h
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# CHECK-NEXT: ^
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.arch armv8.1-a+noras
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esb
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# CHECK: error: instruction requires: ras
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# CHECK-NEXT: esb
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// PR32873: without extra features, '.arch' is currently ignored.
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// Add an unrelated feature to accept the directive.
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.arch armv8+crc
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casa w5, w7, [x19]
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# CHECK: error: instruction requires: lse
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# CHECK-NEXT: casa w5, w7, [x19]
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.arch armv8+crypto
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crc32b w0, w1, w2
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# CHECK: error: instruction requires: crc
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# CHECK-NEXT: crc32b w0, w1, w2
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.arch armv8.1-a+nolse
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casa w5, w7, [x20]
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# CHECK: error: instruction requires: lse
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# CHECK-NEXT: casa w5, w7, [x20]
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