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141144803d
This change attempts to shrink scalar AND, OR and XOR instructions which take an immediate that isn't inlineable. It performs: AND s0, s0, ~(1 << n) -> BITSET0 s0, n OR s0, s0, (1 << n) -> BITSET1 s0, n AND s0, s1, x -> ANDN2 s0, s1, ~x OR s0, s1, x -> ORN2 s0, s1, ~x XOR s0, s1, x -> XNOR s0, s1, ~x In particular, this catches setting and clearing the sign bit for fabs (and x, 0x7ffffffff -> bitset0 x, 31 and or x, 0x80000000 -> bitset1 x, 31). llvm-svn: 348601
50 lines
1.5 KiB
LLVM
50 lines
1.5 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; SI-LABEL: {{^}}s_or_to_orn2:
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; SI: s_orn2_b32 s{{[0-9]+}}, s{{[0-9]+}}, 50
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define amdgpu_kernel void @s_or_to_orn2(i32 addrspace(1)* %out, i32 %in) {
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%x = or i32 %in, -51
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store i32 %x, i32 addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}s_or_to_orn2_imm0:
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; SI: s_orn2_b32 s{{[0-9]+}}, s{{[0-9]+}}, 50
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define amdgpu_kernel void @s_or_to_orn2_imm0(i32 addrspace(1)* %out, i32 %in) {
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%x = or i32 -51, %in
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store i32 %x, i32 addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}s_and_to_andn2:
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; SI: s_andn2_b32 s{{[0-9]+}}, s{{[0-9]+}}, 50
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define amdgpu_kernel void @s_and_to_andn2(i32 addrspace(1)* %out, i32 %in) {
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%x = and i32 %in, -51
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store i32 %x, i32 addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}s_and_to_andn2_imm0:
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; SI: s_andn2_b32 s{{[0-9]+}}, s{{[0-9]+}}, 50
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define amdgpu_kernel void @s_and_to_andn2_imm0(i32 addrspace(1)* %out, i32 %in) {
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%x = and i32 -51, %in
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store i32 %x, i32 addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}s_xor_to_xnor:
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; SI: s_xnor_b32 s{{[0-9]+}}, s{{[0-9]+}}, 50
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define amdgpu_kernel void @s_xor_to_xnor(i32 addrspace(1)* %out, i32 %in) {
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%x = xor i32 %in, -51
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store i32 %x, i32 addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}s_xor_to_xnor_imm0:
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; SI: s_xnor_b32 s{{[0-9]+}}, s{{[0-9]+}}, 50
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define amdgpu_kernel void @s_xor_to_xnor_imm0(i32 addrspace(1)* %out, i32 %in) {
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%x = xor i32 -51, %in
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store i32 %x, i32 addrspace(1)* %out
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ret void
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}
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