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c22abcde1d
Use the 64-bit SGPR base with a 0 offset, since it's 1 fewer instruction to materialize the 0 vs. the 64-bit copy.
20 lines
783 B
LLVM
20 lines
783 B
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10 %s
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declare i32 @llvm.amdgcn.s.get.waveid.in.workgroup() #0
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; GCN-LABEL: {{^}}test_s_get_waveid_in_workgroup:
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; GFX10: global_store_dword
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; GFX10: s_get_waveid_in_workgroup [[DEST:s[0-9]+]]
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; GFX10: s_waitcnt lgkmcnt(0)
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; GFX10: v_mov_b32_e32 [[VDEST:v[0-9]+]], [[DEST]]
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; GFX10: global_store_dword v{{[0-9]+}}, [[VDEST]], s{{\[[0-9]+:[0-9]+\]$}}
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define amdgpu_kernel void @test_s_get_waveid_in_workgroup(i32 addrspace(1)* %out) {
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; Make sure %out is loaded and assiciated wait count already inserted
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store i32 0, i32 addrspace(1)* %out
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%v = call i32 @llvm.amdgcn.s.get.waveid.in.workgroup()
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store i32 %v, i32 addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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